afa8862328
a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt.
349 lines
7.9 KiB
C
349 lines
7.9 KiB
C
/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000, BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#include <sys/param.h> /* XXX trim includes */
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/md_var.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <isa/isavar.h>
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#include <machine/pci_cfgreg.h>
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#include "pcib_if.h"
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static int cfgmech;
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static int devmax;
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int pcireg_cfgopen(void);
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static struct mtx pcicfg_mtx;
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/*
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* Initialise access to PCI configuration space
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*/
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int
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pci_cfgregopen(void)
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{
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static int opened = 0;
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if (opened)
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return (1);
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if (pcireg_cfgopen() == 0)
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return (0);
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mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
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opened = 1;
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return (1);
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}
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/*
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* Read configuration space register
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*/
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u_int32_t
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pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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uint32_t line;
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. Some use
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* numbers in the range 128-254 to indicate something strange and
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* apparently undocumented anywhere. Assume these are completely bogus
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* and map them to 255, which the rest of the PCI code recognizes as
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* as an invalid IRQ.
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*/
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if (reg == PCIR_INTLINE && bytes == 1) {
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line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
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if (line == 0 || line >= 128)
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line = PCI_INVALID_IRQ;
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return (line);
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}
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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}
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/*
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* Write configuration space register
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*/
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void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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}
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/*
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* Route a PCI interrupt
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*/
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int
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pci_cfgintr(int bus, int device, int pin, int oldirq)
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{
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printf("pci_cfgintr: can't route an interrupt to %d:%d INT%c without ACPI\n", bus,
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device, 'A' + pin - 1);
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return (PCI_INVALID_IRQ);
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}
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/*
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* Configuration space access using direct register operations
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*/
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/* enable configuration space accesses and return data port address */
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static int
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pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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{
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int dataport = 0;
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if (bus <= PCI_BUSMAX
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&& slot < devmax
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&& func <= PCI_FUNCMAX
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&& reg <= PCI_REGMAX
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&& bytes != 3
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&& (unsigned) bytes <= 4
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&& (reg & (bytes - 1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, (1 << 31)
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| (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
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outb(CONF2_FORWARD_PORT, bus);
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dataport = 0xc000 | (slot << 8) | reg;
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break;
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}
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}
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return (dataport);
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}
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/* disable configuration space accesses */
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static void
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pci_cfgdisable(void)
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{
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0);
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0);
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outb(CONF2_FORWARD_PORT, 0);
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break;
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}
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}
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static int
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pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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{
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int data = -1;
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int port;
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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data = inb(port);
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break;
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case 2:
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data = inw(port);
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break;
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case 4:
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data = inl(port);
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break;
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}
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pci_cfgdisable();
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}
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mtx_unlock_spin(&pcicfg_mtx);
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return (data);
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}
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static void
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pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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outb(port, data);
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break;
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case 2:
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outw(port, data);
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break;
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case 4:
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outl(port, data);
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break;
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}
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pci_cfgdisable();
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}
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mtx_unlock_spin(&pcicfg_mtx);
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}
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/* check whether the configuration mechanism has been correctly identified */
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static int
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pci_cfgcheck(int maxdev)
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{
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uint32_t id, class;
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uint8_t header;
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uint8_t device;
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int port;
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if (bootverbose)
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printf("pci_cfgcheck:\tdevice ");
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for (device = 0; device < maxdev; device++) {
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if (bootverbose)
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printf("%d ", device);
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port = pci_cfgenable(0, device, 0, 0, 4);
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id = inl(port);
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if (id == 0 || id == 0xffffffff)
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continue;
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port = pci_cfgenable(0, device, 0, 8, 4);
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class = inl(port) >> 8;
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if (bootverbose)
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printf("[class=%06x] ", class);
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if (class == 0 || (class & 0xf870ff) != 0)
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continue;
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port = pci_cfgenable(0, device, 0, 14, 1);
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header = inb(port);
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if (bootverbose)
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printf("[hdr=%02x] ", header);
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if ((header & 0x7e) != 0)
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continue;
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if (bootverbose)
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printf("is there (id=%08x)\n", id);
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pci_cfgdisable();
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return (1);
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}
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if (bootverbose)
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printf("-- nothing found\n");
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pci_cfgdisable();
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return (0);
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}
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static int
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pcireg_cfgopen(void)
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{
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uint32_t mode1res, oldval1;
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uint8_t mode2res, oldval2;
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oldval1 = inl(CONF1_ADDR_PORT);
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if (bootverbose) {
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printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
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oldval1);
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}
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if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
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cfgmech = 1;
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devmax = 32;
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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outb(CONF1_ADDR_PORT + 3, 0);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK);
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if (mode1res) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK1);
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if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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}
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oldval2 = inb(CONF2_ENABLE_PORT);
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if (bootverbose) {
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printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
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oldval2);
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}
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if ((oldval2 & 0xf0) == 0) {
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cfgmech = 2;
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devmax = 16;
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outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
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mode2res = inb(CONF2_ENABLE_PORT);
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outb(CONF2_ENABLE_PORT, oldval2);
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if (bootverbose)
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printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
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mode2res, CONF2_ENABLE_CHK);
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if (mode2res == CONF2_ENABLE_RES) {
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if (bootverbose)
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printf("pci_open(2a):\tnow trying mechanism 2\n");
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if (pci_cfgcheck(16))
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return (cfgmech);
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}
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}
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cfgmech = 0;
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devmax = 0;
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return (cfgmech);
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}
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