b2b734e771
o Eliminate tlb0[] (a s/w copy of TLB0)
- The table contents cannot be maintained reliably in multiple MMU
environments, where asynchronous events (invalidations from other cores)
can change our local TLB0 contents underneath.
- Simplify and optimize TLB flushing: system wide invalidations are
performed using tlbivax instruction (propagates to other cores), for
local MMU invalidations a new optimized routine (assembly) is introduced.
o Improve and simplify TID allocation and management.
- Let each core keep track of its TID allocations.
- Simplify TID recycling, eliminate dead code.
- Drop the now unused powerpc/booke/support.S file.
o Improve page tables management logic.
o Simplify TLB1 manipulation routines.
o Other improvements and polishing.
Obtained from: Freescale, Semihalf
261 lines
7.6 KiB
C
261 lines
7.6 KiB
C
/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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#if defined(AIM)
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/*
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* Page Table Entries
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*/
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#ifndef LOCORE
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/* 32-bit PTE */
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struct pte {
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u_int32_t pte_hi;
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u_int32_t pte_lo;
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};
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struct pteg {
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struct pte pt[8];
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};
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/* 64-bit (long) PTE */
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struct lpte {
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u_int64_t pte_hi;
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u_int64_t pte_lo;
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};
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struct lpteg {
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struct lpte pt[8];
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};
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#endif /* LOCORE */
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/* 32-bit PTE definitions */
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/* High word: */
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#define PTE_VALID 0x80000000
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#define PTE_VSID_SHFT 7
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#define PTE_HID 0x00000040
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#define PTE_API 0x0000003f
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/* Low word: */
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#define PTE_RPGN 0xfffff000
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#define PTE_REF 0x00000100
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#define PTE_CHG 0x00000080
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#define PTE_WIMG 0x00000078
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#define PTE_W 0x00000040
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#define PTE_I 0x00000020
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#define PTE_M 0x00000010
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#define PTE_G 0x00000008
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#define PTE_PP 0x00000003
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#define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */
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#define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */
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#define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */
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#define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */
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#define PTE_RW PTE_BW
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#define PTE_RO PTE_BR
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#define PTE_EXEC 0x00000200 /* pseudo bit in attrs; page is exec */
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/* 64-bit PTE definitions */
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/* High quadword: */
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#define LPTE_VSID_SHIFT 12
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#define LPTE_API 0x0000000000000F80ULL
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#define LPTE_BIG 0x0000000000000004ULL /* 4kb/16Mb page */
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#define LPTE_HID 0x0000000000000002ULL
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#define LPTE_VALID 0x0000000000000001ULL
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/* Low quadword: */
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#define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */
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#define LPTE_RPGN 0xfffffffffffff000ULL
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#define LPTE_REF EXTEND_PTE( PTE_REF )
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#define LPTE_CHG EXTEND_PTE( PTE_CHG )
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#define LPTE_WIMG EXTEND_PTE( PTE_WIMG )
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#define LPTE_W EXTEND_PTE( PTE_W )
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#define LPTE_I EXTEND_PTE( PTE_I )
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#define LPTE_M EXTEND_PTE( PTE_M )
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#define LPTE_G EXTEND_PTE( PTE_G )
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#define LPTE_NOEXEC 0x0000000000000004ULL
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#define LPTE_PP EXTEND_PTE( PTE_PP )
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#define LPTE_SO EXTEND_PTE( PTE_SO ) /* Super. Only */
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#define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */
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#define LPTE_BW EXTEND_PTE( PTE_BW ) /* Supervisor */
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#define LPTE_BR EXTEND_PTE( PTE_BR ) /* Both Read Only */
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#define LPTE_RW LPTE_BW
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#define LPTE_RO LPTE_BR
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#ifndef LOCORE
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typedef struct pte pte_t;
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typedef struct lpte lpte_t;
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#endif /* LOCORE */
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/*
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* Extract bits from address
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*/
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#define ADDR_SR_SHFT 28
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#define ADDR_PIDX 0x0ffff000
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#define ADDR_PIDX_SHFT 12
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#define ADDR_API_SHFT 22
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#define ADDR_API_SHFT64 16
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#define ADDR_POFF 0x00000fff
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/*
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* Bits in DSISR:
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*/
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#define DSISR_DIRECT 0x80000000
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#define DSISR_NOTFOUND 0x40000000
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#define DSISR_PROTECT 0x08000000
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#define DSISR_INVRX 0x04000000
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#define DSISR_STORE 0x02000000
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#define DSISR_DABR 0x00400000
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#define DSISR_SEGMENT 0x00200000
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#define DSISR_EAR 0x00100000
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/*
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* Bits in SRR1 on ISI:
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*/
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#define ISSRR1_NOTFOUND 0x40000000
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#define ISSRR1_DIRECT 0x10000000
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#define ISSRR1_PROTECT 0x08000000
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#define ISSRR1_SEGMENT 0x00200000
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#ifdef _KERNEL
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#ifndef LOCORE
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extern u_int dsisr(void);
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#endif /* _KERNEL */
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#endif /* LOCORE */
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#else
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#include <machine/tlb.h>
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/*
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* 1st level - page table directory (pdir)
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*
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* pdir consists of 1024 entries, each being a pointer to
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* second level entity, i.e. the actual page table (ptbl).
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*/
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#define PDIR_SHIFT 22
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#define PDIR_SIZE (1 << PDIR_SHIFT) /* va range mapped by pdir */
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#define PDIR_MASK (~(PDIR_SIZE - 1))
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#define PDIR_NENTRIES 1024 /* number of page tables in pdir */
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/* Returns pdir entry number for given va */
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#define PDIR_IDX(va) ((va) >> PDIR_SHIFT)
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#define PDIR_ENTRY_SHIFT 2 /* entry size is 2^2 = 4 bytes */
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/*
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* 2nd level - page table (ptbl)
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*
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* Page table covers 1024 page table entries. Page
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* table entry (pte) is 32 bit wide and defines mapping
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* for a single page.
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*/
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#define PTBL_SHIFT PAGE_SHIFT
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#define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */
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#define PTBL_MASK ((PDIR_SIZE - 1) & ~PAGE_MASK)
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#define PTBL_NENTRIES 1024 /* number of pages mapped by ptbl */
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/* Returns ptbl entry number for given va */
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#define PTBL_IDX(va) (((va) & PTBL_MASK) >> PTBL_SHIFT)
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/* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */
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#define PTBL_PAGES 2
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#define PTBL_ENTRY_SHIFT 3 /* entry size is 2^3 = 8 bytes */
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/*
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* Flags for pte_remove() routine.
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*/
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#define PTBL_HOLD 0x00000001 /* do not unhold ptbl pages */
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#define PTBL_UNHOLD 0x00000002 /* unhold and attempt to free ptbl pages */
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#define PTBL_HOLD_FLAG(pmap) (((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD)
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/*
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* Page Table Entry definitions and macros.
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*/
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#ifndef LOCORE
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struct pte {
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vm_offset_t rpn;
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uint32_t flags;
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};
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typedef struct pte pte_t;
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#endif
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/* RPN mask, TLB0 4K pages */
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#define PTE_PA_MASK PAGE_MASK
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/* PTE bits assigned to MAS2, MAS3 flags */
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#define PTE_W MAS2_W
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#define PTE_I MAS2_I
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#define PTE_M MAS2_M
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#define PTE_G MAS2_G
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#define PTE_MAS2_MASK (MAS2_G | MAS2_M | MAS2_I | MAS2_W)
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#define PTE_MAS3_SHIFT 8
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#define PTE_UX (MAS3_UX << PTE_MAS3_SHIFT)
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#define PTE_SX (MAS3_SX << PTE_MAS3_SHIFT)
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#define PTE_UW (MAS3_UW << PTE_MAS3_SHIFT)
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#define PTE_SW (MAS3_SW << PTE_MAS3_SHIFT)
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#define PTE_UR (MAS3_UR << PTE_MAS3_SHIFT)
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#define PTE_SR (MAS3_SR << PTE_MAS3_SHIFT)
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#define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \
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| MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT)
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/* Other PTE flags */
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#define PTE_VALID 0x80000000 /* Valid */
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#define PTE_MODIFIED 0x40000000 /* Modified */
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#define PTE_WIRED 0x20000000 /* Wired */
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#define PTE_MANAGED 0x10000000 /* Managed */
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#define PTE_FAKE 0x08000000 /* Ficticious */
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#define PTE_REFERENCED 0x04000000 /* Referenced */
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/* Macro argument must of pte_t type. */
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#define PTE_PA(pte) ((pte)->rpn & ~PTE_PA_MASK)
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#define PTE_ISVALID(pte) ((pte)->flags & PTE_VALID)
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#define PTE_ISWIRED(pte) ((pte)->flags & PTE_WIRED)
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#define PTE_ISMANAGED(pte) ((pte)->flags & PTE_MANAGED)
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#define PTE_ISFAKE(pte) ((pte)->flags & PTE_FAKE)
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#define PTE_ISMODIFIED(pte) ((pte)->flags & PTE_MODIFIED)
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#define PTE_ISREFERENCED(pte) ((pte)->flags & PTE_REFERENCED)
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#endif /* #elif defined(E500) */
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#endif /* _MACHINE_PTE_H_ */
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