f11c7f6305
The isci driver is for the integrated SAS controller in the Intel C600 (Patsburg) chipset. Source files in sys/dev/isci directory are FreeBSD-specific, and sys/dev/isci/scil subdirectory contains an OS-agnostic library (SCIL) published by Intel to control the SAS controller. This library is used primarily as-is in this driver, with some post-processing to better integrate into the kernel build environment. isci.4 and a README in the sys/dev/isci directory contain a few additional details. This driver is only built for amd64 and i386 targets. Sponsored by: Intel Reviewed by: scottl Approved by: scottl
309 lines
9.3 KiB
C
309 lines
9.3 KiB
C
/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SCIF_SAS_CONTROLLER_H_
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#define _SCIF_SAS_CONTROLLER_H_
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/**
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* @file
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*
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* @brief This file contains the protected interface structures, constants,
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* and methods for the SCIF_SAS_CONTROLLER object.
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif // __cplusplus
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#include <dev/isci/scil/sci_types.h>
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#include <dev/isci/scil/sci_abstract_list.h>
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#include <dev/isci/scil/sci_controller_constants.h>
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#include <dev/isci/scil/sci_memory_descriptor_list.h>
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#include <dev/isci/scil/sci_base_controller.h>
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#include <dev/isci/scil/scif_controller.h>
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#include <dev/isci/scil/scif_config_parameters.h>
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#include <dev/isci/scil/scif_sas_domain.h>
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#include <dev/isci/scil/scif_sas_io_request.h>
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#include <dev/isci/scil/scif_sas_task_request.h>
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#include <dev/isci/scil/scif_sas_constants.h>
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#include <dev/isci/scil/sci_pool.h>
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#include <dev/isci/scil/scif_sas_internal_io_request.h>
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#include <dev/isci/scil/scif_sas_high_priority_request_queue.h>
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#include <dev/isci/scil/scif_sas_smp_phy.h>
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// Currently there is only a need for 1 memory descriptor. This descriptor
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// describes the internal IO request memory.
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#define SCIF_SAS_MAX_MEMORY_DESCRIPTORS 1
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enum _SCIF_SAS_MAX_MEMORY_DESCRIPTORS
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{
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SCIF_SAS_MDE_INTERNAL_IO = 0
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};
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/**
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* @struct SCIF_SAS_CONTROLLER
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*
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* @brief The SCI SAS Framework controller object abstracts storage controller
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* level behavior for the framework component.
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*/
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typedef struct SCIF_SAS_CONTROLLER
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{
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/**
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* The SCI_BASE_CONTROLLER is the parent object for the SCIF_SAS_CONTROLLER
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* object.
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*/
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SCI_BASE_CONTROLLER_T parent;
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/**
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* This field contains the handle for the SCI Core controller object that
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* is managed by this framework controller.
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*/
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SCI_CONTROLLER_HANDLE_T core_object;
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/**
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* This field references the list of state specific handler methods to
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* be utilized for this controller instance.
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*/
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SCI_BASE_CONTROLLER_STATE_HANDLER_T * state_handlers;
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/**
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* This field contains the memory desciptors defining the physical
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* memory requirements for this controller.
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*/
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SCI_PHYSICAL_MEMORY_DESCRIPTOR_T mdes[SCIF_SAS_MAX_MEMORY_DESCRIPTORS];
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/**
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* This field contains the SAS domain objects managed by this controller.
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*/
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SCIF_SAS_DOMAIN_T domains[SCI_MAX_DOMAINS];
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/**
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* This field represents the pool of available remote device objects
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* supported by the controller.
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*/
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SCI_ABSTRACT_ELEMENT_POOL_T free_remote_device_pool;
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/**
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* This field contains the maximum number of abstract elements that
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* can be placed in the pool.
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*/
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SCI_ABSTRACT_ELEMENT_T remote_device_pool_elements[SCI_MAX_REMOTE_DEVICES];
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/**
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* This field provides the controller object a scratch area to indicate
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* status of an ongoing operation.
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*/
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SCI_STATUS operation_status;
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/**
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* This field will contain an user specified parameter information
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* to be utilized by the framework.
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*/
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SCIF_USER_PARAMETERS_T user_parameters;
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/**
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* This field records the index for the current domain to clear affiliation
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* EA SATA remote devices, during the controller stop process.
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*/
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U8 current_domain_to_clear_affiliation;
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U32 internal_request_entries;
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/**
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* This field provides a pool to manage the memory resource for all internal
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* requests.
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* requests.
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*/
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SCI_POOL_CREATE(
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internal_request_memory_pool,
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POINTER_UINT,
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SCIF_SAS_MAX_INTERNAL_REQUEST_COUNT
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);
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/**
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* This field provides a queue for built internal requests waiting to be
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* started.
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*/
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SCIF_SAS_HIGH_PRIORITY_REQUEST_QUEUE_T hprq;
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/**
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* This represents the number of available SMP phy objects that can
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* be managed by the framework.
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*/
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SCIF_SAS_SMP_PHY_T smp_phy_array[SCIF_SAS_SMP_PHY_COUNT];
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/**
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* This field provides a list to manage the memory resource for all
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* smp_phy objects.
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*/
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SCI_FAST_LIST_T smp_phy_memory_list;
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#if !defined(DISABLE_INTERRUPTS)
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/**
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* This field saves the interrupt coalescing count before changing interrupt
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* coalescence.
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*/
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U16 saved_interrupt_coalesce_number;
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/**
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* This field saves the interrupt coalescing timeout values in micorseconds
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* before changing interrupt coalescence.
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*/
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U32 saved_interrupt_coalesce_timeout;
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#endif // !defined(DISABLE_INTERRUPTS)
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} SCIF_SAS_CONTROLLER_T;
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extern SCI_BASE_STATE_T scif_sas_controller_state_table[];
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extern SCI_BASE_CONTROLLER_STATE_HANDLER_T
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scif_sas_controller_state_handler_table[];
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SCI_STATUS scif_sas_controller_continue_io(
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SCI_CONTROLLER_HANDLE_T controller,
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SCI_REMOTE_DEVICE_HANDLE_T remote_device,
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SCI_IO_REQUEST_HANDLE_T io_request
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);
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void scif_sas_controller_destruct(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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void * scif_sas_controller_allocate_internal_request(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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void scif_sas_controller_free_internal_request(
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SCIF_SAS_CONTROLLER_T * fw_controller,
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void * fw_internal_request_buffer
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);
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void scif_sas_controller_start_high_priority_io(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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BOOL scif_sas_controller_sufficient_resource(
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SCIF_SAS_CONTROLLER_T *fw_controller
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);
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SCI_STATUS scif_sas_controller_complete_high_priority_io(
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SCIF_SAS_CONTROLLER_T * fw_controller,
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SCIF_SAS_REMOTE_DEVICE_T * remote_device,
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SCIF_SAS_REQUEST_T * io_request
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);
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SCIF_SAS_SMP_PHY_T * scif_sas_controller_allocate_smp_phy(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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void scif_sas_controller_free_smp_phy(
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SCIF_SAS_CONTROLLER_T * fw_controller,
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SCIF_SAS_SMP_PHY_T * smp_phy
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);
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SCI_STATUS scif_sas_controller_clear_affiliation(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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SCI_STATUS scif_sas_controller_continue_to_stop(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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void scif_sas_controller_set_default_config_parameters(
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SCIF_SAS_CONTROLLER_T * this_controller
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);
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SCI_STATUS scif_sas_controller_release_resource(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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void scif_sas_controller_build_mdl(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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#if !defined(DISABLE_INTERRUPTS)
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void scif_sas_controller_save_interrupt_coalescence(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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void scif_sas_controller_restore_interrupt_coalescence(
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SCIF_SAS_CONTROLLER_T * fw_controller
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);
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#else // !defined(DISABLE_INTERRUPTS)
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#define scif_sas_controller_save_interrupt_coalescence(controller)
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#define scif_sas_controller_restore_interrupt_coalescence(controller)
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#endif // !defined(DISABLE_INTERRUPTS)
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#ifdef SCI_LOGGING
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void scif_sas_controller_initialize_state_logging(
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SCIF_SAS_CONTROLLER_T *this_controller
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);
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void scif_sas_controller_deinitialize_state_logging(
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SCIF_SAS_CONTROLLER_T *this_controller
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);
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#else // SCI_LOGGING
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#define scif_sas_controller_initialize_state_logging(x)
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#define scif_sas_controller_deinitialize_state_logging(x)
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#endif // SCI_LOGGING
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#ifdef __cplusplus
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}
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#endif // __cplusplus
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#endif // _SCIF_SAS_CONTROLLER_H_
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