Conrad Meyer 194446f9b7 x86: Decode AMD "Extended Feature Extensions ID EBX" bits ... In particular, this determines CPU support for the CLZERO instruction. (No, I am not making this name up.) Sponsored by: Dell EMC Isilon		2017-09-20 18:30:37 +00:00
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acpica	acpi/srat: zero the SRAT cpu array	2017-09-04 10:08:42 +00:00
bios
cpufreq	cpufreq(4) hwpstate: Yield CPU awaiting frequency change	2017-09-07 20:20:12 +00:00
include	x86: Decode AMD "Extended Feature Extensions ID EBX" bits	2017-09-20 18:30:37 +00:00
iommu	Use IOAPIC PCI rid as the interrupt TLP source id for DMAR interrupt	2017-09-08 19:45:37 +00:00
isa	Stop calling atrtc_set() from the xen timer clock_settime() method. That	2017-08-11 19:02:11 +00:00
pci	Enhance qpi.c to make it usable on all Core-microarchitecture Xeons.	2017-09-08 19:51:03 +00:00
x86	x86: Decode AMD "Extended Feature Extensions ID EBX" bits	2017-09-20 18:30:37 +00:00
xen	apic_enumerator: only set mp_ncpus and mp_maxid at probe cpus phase	2017-08-10 09:15:18 +00:00