118 lines
5.5 KiB
Diff
118 lines
5.5 KiB
Diff
Pull in r200131 from upstream llvm trunk (by Jakob Stoklund Olesen):
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Only generate the popc instruction for SPARC CPUs that implement it.
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The popc instruction is defined in the SPARCv9 instruction set
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architecture, but it was emulated on CPUs older than Niagara 2.
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Introduced here: http://svnweb.freebsd.org/changeset/base/262261
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Index: lib/Target/Sparc/SparcISelLowering.cpp
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===================================================================
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--- lib/Target/Sparc/SparcISelLowering.cpp
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+++ lib/Target/Sparc/SparcISelLowering.cpp
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@@ -1461,7 +1461,8 @@ SparcTargetLowering::SparcTargetLowering(TargetMac
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
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- setOperationAction(ISD::CTPOP, MVT::i64, Legal);
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+ if (Subtarget->usePopc())
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+ setOperationAction(ISD::CTPOP, MVT::i64, Legal);
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setOperationAction(ISD::CTTZ , MVT::i64, Expand);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
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setOperationAction(ISD::CTLZ , MVT::i64, Expand);
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@@ -1567,7 +1568,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMac
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setStackPointerRegisterToSaveRestore(SP::O6);
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- if (Subtarget->isV9())
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+ if (Subtarget->isV9() && Subtarget->usePopc())
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setOperationAction(ISD::CTPOP, MVT::i32, Legal);
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if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
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Index: lib/Target/Sparc/Sparc.td
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===================================================================
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--- lib/Target/Sparc/Sparc.td
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+++ lib/Target/Sparc/Sparc.td
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@@ -34,6 +34,9 @@ def FeatureHardQuad
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: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
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"Enable quad-word floating point instructions">;
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+def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
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+ "Use the popc (population count) instruction">;
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+
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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@@ -69,9 +72,9 @@ def : Proc<"v9", [FeatureV9]>;
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def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
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def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
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def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated]>;
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-def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated]>;
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-def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated]>;
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-def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated]>;
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+def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc]>;
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+def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc]>;
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+def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc]>;
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def SparcAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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Index: lib/Target/Sparc/SparcSubtarget.h
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===================================================================
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--- lib/Target/Sparc/SparcSubtarget.h
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+++ lib/Target/Sparc/SparcSubtarget.h
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@@ -30,6 +30,7 @@ class SparcSubtarget : public SparcGenSubtargetInf
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bool IsVIS;
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bool Is64Bit;
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bool HasHardQuad;
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+ bool UsePopc;
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public:
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SparcSubtarget(const std::string &TT, const std::string &CPU,
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@@ -39,6 +40,7 @@ class SparcSubtarget : public SparcGenSubtargetInf
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bool isVIS() const { return IsVIS; }
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bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
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bool hasHardQuad() const { return HasHardQuad; }
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+ bool usePopc() const { return UsePopc; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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Index: lib/Target/Sparc/SparcSubtarget.cpp
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===================================================================
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--- lib/Target/Sparc/SparcSubtarget.cpp
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+++ lib/Target/Sparc/SparcSubtarget.cpp
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@@ -31,7 +31,8 @@ SparcSubtarget::SparcSubtarget(const std::string &
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V8DeprecatedInsts(false),
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IsVIS(false),
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Is64Bit(is64Bit),
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- HasHardQuad(false) {
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+ HasHardQuad(false),
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+ UsePopc(false) {
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// Determine default and user specified characteristics
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std::string CPUName = CPU;
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Index: test/CodeGen/SPARC/ctpop.ll
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===================================================================
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--- test/CodeGen/SPARC/ctpop.ll
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+++ test/CodeGen/SPARC/ctpop.ll
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@@ -1,13 +1,13 @@
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; RUN: llc < %s -march=sparc -mattr=-v9 | FileCheck %s -check-prefix=V8
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-; RUN: llc < %s -march=sparc -mattr=+v9 | FileCheck %s -check-prefix=V9
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-; RUN: llc < %s -march=sparc -mcpu=v9 | FileCheck %s -check-prefix=V9
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-; RUN: llc < %s -march=sparc -mcpu=ultrasparc | FileCheck %s -check-prefix=V9
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-; RUN: llc < %s -march=sparc -mcpu=ultrasparc3 | FileCheck %s -check-prefix=V9
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-; RUN: llc < %s -march=sparc -mcpu=niagara | FileCheck %s -check-prefix=V9
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+; RUN: llc < %s -march=sparc -mattr=+v9,+popc | FileCheck %s -check-prefix=V9
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+; RUN: llc < %s -march=sparc -mcpu=v9 | FileCheck %s -check-prefix=V8
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+; RUN: llc < %s -march=sparc -mcpu=ultrasparc | FileCheck %s -check-prefix=V8
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+; RUN: llc < %s -march=sparc -mcpu=ultrasparc3 | FileCheck %s -check-prefix=V8
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+; RUN: llc < %s -march=sparc -mcpu=niagara | FileCheck %s -check-prefix=V8
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; RUN: llc < %s -march=sparc -mcpu=niagara2 | FileCheck %s -check-prefix=V9
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; RUN: llc < %s -march=sparc -mcpu=niagara3 | FileCheck %s -check-prefix=V9
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; RUN: llc < %s -march=sparc -mcpu=niagara4 | FileCheck %s -check-prefix=V9
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-; RUN: llc < %s -march=sparcv9 | FileCheck %s -check-prefix=SPARC64
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+; RUN: llc < %s -march=sparcv9 -mattr=+popc | FileCheck %s -check-prefix=SPARC64
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declare i32 @llvm.ctpop.i32(i32)
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