90 lines
3.5 KiB
Diff
90 lines
3.5 KiB
Diff
Pull in r202422 from upstream llvm trunk (by Roman Divacky):
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Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding
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expensive libcall. Also, Qp_neg is not implemented on at least
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FreeBSD. This is also what gcc is doing.
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Introduced here: http://svnweb.freebsd.org/changeset/base/262582
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Index: lib/Target/Sparc/SparcISelLowering.cpp
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===================================================================
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--- lib/Target/Sparc/SparcISelLowering.cpp
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+++ lib/Target/Sparc/SparcISelLowering.cpp
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@@ -2643,24 +2643,16 @@ static SDValue LowerF128Store(SDValue Op, Selectio
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&OutChains[0], 2);
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}
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-static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG,
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- const SparcTargetLowering &TLI,
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- bool is64Bit) {
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- if (Op.getValueType() == MVT::f64)
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- return LowerF64Op(Op, DAG, ISD::FNEG);
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- if (Op.getValueType() == MVT::f128)
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- return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1);
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- return Op;
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-}
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+static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
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+ assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) && "invalid");
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-static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
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if (Op.getValueType() == MVT::f64)
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- return LowerF64Op(Op, DAG, ISD::FABS);
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+ return LowerF64Op(Op, DAG, Op.getOpcode());
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if (Op.getValueType() != MVT::f128)
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return Op;
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- // Lower fabs on f128 to fabs on f64
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- // fabs f128 => fabs f64:sub_even64, fmov f64:sub_odd64
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+ // Lower fabs/fneg on f128 to fabs/fneg on f64
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+ // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
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SDLoc dl(Op);
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SDValue SrcReg128 = Op.getOperand(0);
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@@ -2671,7 +2663,7 @@ static SDValue LowerF128Store(SDValue Op, Selectio
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if (isV9)
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Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
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else
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- Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS);
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+ Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode());
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SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
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dl, MVT::f128), 0);
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@@ -2792,7 +2784,6 @@ SDValue SparcTargetLowering::
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LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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bool hasHardQuad = Subtarget->hasHardQuad();
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- bool is64Bit = Subtarget->is64Bit();
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bool isV9 = Subtarget->isV9();
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switch (Op.getOpcode()) {
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@@ -2835,8 +2826,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) cons
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getLibcallName(RTLIB::DIV_F128), 2);
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case ISD::FSQRT: return LowerF128Op(Op, DAG,
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getLibcallName(RTLIB::SQRT_F128),1);
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- case ISD::FNEG: return LowerFNEG(Op, DAG, *this, is64Bit);
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- case ISD::FABS: return LowerFABS(Op, DAG, isV9);
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+ case ISD::FABS:
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+ case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
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case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
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case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
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case ISD::ADDC:
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Index: test/CodeGen/SPARC/fp128.ll
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===================================================================
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--- test/CodeGen/SPARC/fp128.ll
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+++ test/CodeGen/SPARC/fp128.ll
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@@ -232,3 +232,14 @@ entry:
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store i32 %3, i32* %4, align 8
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ret void
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}
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+
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+; SOFT-LABEL: f128_neg
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+; SOFT: fnegs
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+
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+define void @f128_neg(fp128* noalias sret %scalar.result, fp128* byval %a) {
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+entry:
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+ %0 = load fp128* %a, align 8
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+ %1 = fsub fp128 0xL00000000000000008000000000000000, %0
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+ store fp128 %1, fp128* %scalar.result, align 8
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+ ret void
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+}
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