819c857f10
to apply with the same patch options onto a fresh upstream llvm/clang 3.4.1 checkout, and use approximately the same header tempate for them. MFC after: 3 days
79 lines
2.6 KiB
Diff
79 lines
2.6 KiB
Diff
Pull in r216989 from upstream llvm trunk (by Renato Golin):
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MFV: Only emit movw on ARMv6T2+
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Pull in r216990 from upstream llvm trunk (by Renato Golin):
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Missing test from r216989
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Building for the FreeBSD default target ARMv6 was emitting movw ASM on certain
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test cases (found building qmake4/5 for ARM). Don't do that, moreover, the AS
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in base doesn't understand this instruction for this target. One would need
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to use --integrated-as to get this to build if desired.
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Introduced here: http://svnweb.freebsd.org/changeset/base/271025
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Index: lib/Target/ARM/ARMInstrInfo.td
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===================================================================
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--- lib/Target/ARM/ARMInstrInfo.td
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+++ lib/Target/ARM/ARMInstrInfo.td
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@@ -3248,7 +3248,8 @@
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def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
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(SBCri GPR:$src, so_imm_not:$imm)>;
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def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
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- (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
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+ (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
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+ Requires<[IsARM, HasV6T2]>;
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// Note: These are implemented in C++ code, because they have to generate
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// ADD/SUBrs instructions, which use a complex pattern that a xform function
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Index: test/CodeGen/ARM/carry.ll
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===================================================================
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--- test/CodeGen/ARM/carry.ll
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+++ test/CodeGen/ARM/carry.ll
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@@ -1,4 +1,4 @@
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-; RUN: llc < %s -march=arm | FileCheck %s
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+; RUN: llc < %s -mtriple=armv6t2-eabi | FileCheck %s
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define i64 @f1(i64 %a, i64 %b) {
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; CHECK-LABEL: f1:
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Index: test/CodeGen/ARM/pr18364-movw.ll
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===================================================================
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--- test/CodeGen/ARM/pr18364-movw.ll
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+++ test/CodeGen/ARM/pr18364-movw.ll
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@@ -0,0 +1,34 @@
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+; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
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+; RUN: llc < %s -mtriple=armv6 | FileCheck %s --check-prefix=V6
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+; RUN: llc < %s -mtriple=armv6t2 | FileCheck %s --check-prefix=V6T2
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+; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=V7
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+; PR18364
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+
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+define i64 @f() #0 {
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+entry:
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+; V5-NOT: movw
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+; V6-NOT: movw
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+; V6T2: movw
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+; V7: movw
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+ %y = alloca i64, align 8
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+ %z = alloca i64, align 8
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+ store i64 1, i64* %y, align 8
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+ store i64 11579764786944, i64* %z, align 8
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+ %0 = load i64* %y, align 8
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+ %1 = load i64* %z, align 8
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+ %sub = sub i64 %0, %1
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+ ret i64 %sub
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+}
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+
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+define i64 @g(i64 %a, i32 %b) #0 {
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+entry:
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+; V5-NOT: movw
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+; V6-NOT: movw
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+; V6T2: movw
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+; V7: movw
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+ %0 = mul i64 %a, 86400000
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+ %mul = add i64 %0, -210866803200000
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+ %conv = sext i32 %b to i64
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+ %add = add nsw i64 %mul, %conv
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+ ret i64 %add
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+}
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