1024 lines
33 KiB
Groff
1024 lines
33 KiB
Groff
.\" Copyright (c) 2012 Hiren Panchasara <hiren.panchasara@gmail.com>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd October 18, 2012
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.Dt PMC.SANDYBRIDGEXEON 3
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.Os
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.Sh NAME
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.Nm pmc.sandybridgexeon
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.Nd measurement events for
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.Tn Intel
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.Tn Sandy Bridge Xeon
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel
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.Tn "Sandy Bridge Xeon"
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CPUs contain PMCs conforming to version 2 of the
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.Tn Intel
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performance measurement architecture.
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These CPUs may contain up to two classes of PMCs:
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.Bl -tag -width "Li PMC_CLASS_IAP"
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.It Li PMC_CLASS_IAF
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Fixed-function counters that count only one hardware event per counter.
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.It Li PMC_CLASS_IAP
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Programmable counters that may be configured to count one of a defined
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set of hardware events.
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.El
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.Pp
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The number of PMCs available in each class and their widths need to be
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determined at run time by calling
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.Xr pmc_cpuinfo 3 .
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.Pp
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Intel Sandy Bridge Xeon PMCs are documented in
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.Rs
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.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
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.%T "Volume 3B: System Programming Guide, Part 2"
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.%N "Order Number: 253669-043US"
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.%D August 2012
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.%Q "Intel Corporation"
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.Re
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.Ss SANDYBRIDGE XEON FIXED FUNCTION PMCS
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These PMCs and their supported events are documented in
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.Xr pmc.iaf 3 .
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.Ss SANDYBRIDGE XEON PROGRAMMABLE PMCS
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The programmable PMCs support the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta Yes
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.It PMC_CAP_INVERT Ta Yes
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta Yes
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta Yes
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.It PMC_CAP_USER Ta Yes
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for these PMCs support the following common
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qualifiers:
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.Bl -tag -width indent
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.It Li rsp= Ns Ar value
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Configure the Off-core Response bits.
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.Bl -tag -width indent
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.It Li REQ_DMND_DATA_RD
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Counts the number of demand and DCU prefetch data reads of full and partial
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cachelines as well as demand data page table entry cacheline reads. Does not
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count L2 data read prefetches or instruction fetches.
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.It Li REQ_DMND_RFO
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Counts the number of demand and DCU prefetch reads for ownership (RFO)
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requests generated by a write to data cacheline. Does not count L2 RFO
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prefetches.
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.It Li REQ_DMND_IFETCH
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Counts the number of demand and DCU prefetch instruction cacheline reads.
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Does not count L2 code read prefetches.
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.It Li REQ_WB
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Counts the number of writeback (modified to exclusive) transactions.
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.It Li REQ_PF_DATA_RD
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Counts the number of data cacheline reads generated by L2 prefetchers.
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.It Li REQ_PF_RFO
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Counts the number of RFO requests generated by L2 prefetchers.
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.It Li REQ_PF_IFETCH
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Counts the number of code reads generated by L2 prefetchers.
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.It Li REQ_PF_LLC_DATA_RD
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L2 prefetcher to L3 for loads.
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.It Li REQ_PF_LLC_RFO
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RFO requests generated by L2 prefetcher
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.It Li REQ_PF_LLC_IFETCH
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L2 prefetcher to L3 for instruction fetches.
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.It Li REQ_BUS_LOCKS
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Bus lock and split lock requests.
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.It Li REQ_STRM_ST
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Streaming store requests.
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.It Li REQ_OTHER
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Any other request that crosses IDI, including I/O.
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.It Li RES_ANY
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Catch all value for any response types.
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.It Li RES_SUPPLIER_NO_SUPP
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No Supplier Information available.
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.It Li RES_SUPPLIER_LLC_HITM
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M-state initial lookup stat in L3.
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.It Li RES_SUPPLIER_LLC_HITE
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E-state.
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.It Li RES_SUPPLIER_LLC_HITS
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S-state.
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.It Li RES_SUPPLIER_LLC_HITF
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F-state.
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.It Li RES_SUPPLIER_LOCAL
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Local DRAM Controller.
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.It Li RES_SNOOP_SNP_NONE
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No details on snoop-related information.
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.It Li RES_SNOOP_SNP_NO_NEEDED
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No snoop was needed to satisfy the request.
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.It Li RES_SNOOP_SNP_MISS
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A snoop was needed and it missed all snooped caches:
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-For LLC Hit, ReslHitl was returned by all cores
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-For LLC Miss, Rspl was returned by all sockets and data was returned from
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DRAM.
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.It Li RES_SNOOP_HIT_NO_FWD
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A snoop was needed and it hits in at least one snooped cache. Hit denotes a
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cache-line was valid before snoop effect. This includes:
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-Snoop Hit w/ Invalidation (LLC Hit, RFO)
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-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
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-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
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In the LLC Miss case, data is returned from DRAM.
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.It Li RES_SNOOP_HIT_FWD
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A snoop was needed and data was forwarded from a remote socket.
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This includes:
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-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
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.It Li RES_SNOOP_HITM
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A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
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cache-line was in modified state before effect as a results of snoop. This
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includes:
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-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
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-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
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-Snoop MtoS (LLC Hit, IFetch/Data_RD).
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.It Li RES_NON_DRAM
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Target was non-DRAM system address. This includes MMIO transactions.
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.El
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.It Li cmask= Ns Ar value
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Configure the PMC to increment only if the number of configured
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events measured in a cycle is greater than or equal to
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.Ar value .
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.It Li edge
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Configure the PMC to count the number of de-asserted to asserted
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transitions of the conditions expressed by the other qualifiers.
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If specified, the counter will increment only once whenever a
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condition becomes true, irrespective of the number of clocks during
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which the condition remains true.
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.It Li inv
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Invert the sense of comparison when the
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.Dq Li cmask
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qualifier is present, making the counter increment when the number of
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events per cycle is less than the value specified by the
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.Dq Li cmask
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qualifier.
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.It Li os
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Configure the PMC to count events happening at processor privilege
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level 0.
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.It Li usr
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Configure the PMC to count events occurring at privilege levels 1, 2
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or 3.
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.El
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.Pp
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If neither of the
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.Dq Li os
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or
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.Dq Li usr
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qualifiers are specified, the default is to enable both.
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.Ss Event Specifiers (Programmable PMCs)
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Sandy Bridge Xeon programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li LD_BLOCKS.DATA_UNKNOWN
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.Pq Event 03H , Umask 01H
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blocked loads due to store buffer blocks with unknown data.
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.It Li LD_BLOCKS.STORE_FORWARD
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.Pq Event 03H , Umask 02H
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loads blocked by overlapping with store buffer that cannot
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be forwarded .
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.It Li LD_BLOCKS.NO_SR
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.Pq Event 03H , Umask 08H
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# of Split loads blocked due to resource not available.
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.It Li LD_BLOCKS.ALL_BLOCK
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.Pq Event 03H , Umask 10H
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Number of cases where any load is blocked but has no
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DCU miss.
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.It Li MISALIGN_MEM_REF.LOADS
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.Pq Event 05H , Umask 01H
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Speculative cache-line split load uops dispatched to
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L1D.
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.It Li MISALIGN_MEM_REF.STORES
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.Pq Event 05H , Umask 02H
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Speculative cache-line split Store- address uops
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dispatched to L1D.
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.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
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.Pq Event 07H , Umask 01H
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False dependencies in MOB due to partial compare on
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address.
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.It Li LD_BLOCKS_PARTIAL.ALL_STALL_BLOCK
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.Pq Event 07H , Umask 08H
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The number of times that load operations are temporarily
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blocked because of older stores, with addresses that are
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not yet known. A load operation may incur more than one
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block of this type.
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.It Li TLB_LOAD_MISSES.MISS_CAUSES_A_WALK
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.Pq Event 08H , Umask 01H
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Misses in all TLB levels that cause a page walk of any
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page size.
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.It Li TLB_LOAD_MISSES.WALK_COMPLETED
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.Pq Event 08H , Umask 02H
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Misses in all TLB levels that caused page walk completed
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of any size.
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.It Li DTLB_LOAD_MISSES.WALK_DURATION
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.Pq Event 08H , Umask 04H
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Cycle PMH is busy with a walk.
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.It Li DTLB_LOAD_MISSES.STLB_HIT
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.Pq Event 08H , Umask 10H
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Number of cache load STLB hits. No page walk.
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.It Li INT_MISC.RECOVERY_CYCLES
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.Pq Event 0DH , Umask 03H
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Cycles waiting to recover after Machine Clears or EClear.
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Set Cmask= 1.
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.It Li INT_MISC.RAT_STALL_CYCLES
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.Pq Event 0DH , Umask 40H
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Cycles RAT external stall is sent to IDQ for this thread.
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.It Li UOPS_ISSUED.ANY
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.Pq Event 0EH , Umask 01H
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Increments each cycle the # of Uops issued by the
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RAT to RS.
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Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles
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of this core.
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.It Li FP_COMP_OPS_EXE.X87
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.Pq Event 10H , Umask 01H
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Counts number of X87 uops executed.
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.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE
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.Pq Event 10H , Umask 10H
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Counts number of SSE* double precision FP packed
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uops executed.
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.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE
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.Pq Event 10H , Umask 20H
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Counts number of SSE* single precision FP scalar
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uops executed.
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.It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE
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.Pq Event 10H , Umask 40H
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Counts number of SSE* single precision FP packed
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uops executed.
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.It Li FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE
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.Pq Event 10H , Umask 80H
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Counts number of SSE* double precision FP scalar
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uops executed.
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.It Li SIMD_FP_256.PACKED_SINGLE
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.Pq Event 11H , Umask 01H
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Counts 256-bit packed single-precision floating-
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point instructions.
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.It Li SIMD_FP_256.PACKED_DOUBLE
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.Pq Event 11H , Umask 02H
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Counts 256-bit packed double-precision floating-
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point instructions.
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.It Li ARITH.FPU_DIV_ACTIVE
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.Pq Event 14H , Umask 01H
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Cycles that the divider is active, includes INT and FP.
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Set 'edge =1, cmask=1' to count the number of
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divides.
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.It Li INSTS_WRITTEN_TO_IQ.INSTS
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.Pq Event 17H , Umask 01H
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Counts the number of instructions written into the
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IQ every cycle.
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.It Li L2_RQSTS.DEMAND_DATA_RD_HIT
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.Pq Event 24H , Umask 01H
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Demand Data Read requests that hit L2 cache.
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.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
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.Pq Event 24H , Umask 03H
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Counts any demand and L1 HW prefetch data load
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requests to L2.
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.It Li L2_RQSTS.RFO_HITS
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.Pq Event 24H , Umask 04H
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Counts the number of store RFO requests that
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hit the L2 cache.
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.It Li L2_RQSTS.RFO_MISS
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.Pq Event 24H , Umask 08H
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Counts the number of store RFO requests that
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miss the L2 cache.
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.It Li L2_RQSTS.ALL_RFO
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.Pq Event 24H , Umask 0CH
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Counts all L2 store RFO requests.
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.It Li L2_RQSTS.CODE_RD_HIT
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.Pq Event 24H , Umask 10H
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Number of instruction fetches that hit the L2
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cache.
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.It Li L2_RQSTS.CODE_RD_MISS
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.Pq Event 24H , Umask 20H
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Number of instruction fetches that missed the L2
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cache.
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.It Li L2_RQSTS.ALL_CODE_RD
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.Pq Event 24H , Umask 30H
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Counts all L2 code requests.
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.It Li L2_RQSTS.PF_HIT
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.Pq Event 24H , Umask 40H
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Requests from L2 Hardware prefetcher that hit L2.
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.It Li L2_RQSTS.PF_MISS
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.Pq Event 24H , Umask 80H
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Requests from L2 Hardware prefetcher that missed
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L2.
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.It Li L2_RQSTS.ALL_PF
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.Pq Event 24H , Umask C0H
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Any requests from L2 Hardware prefetchers.
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.It Li L2_STORE_LOCK_RQSTS.MISS
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.Pq Event 27H , Umask 01H
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ROs that miss cache lines.
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.It Li L2_STORE_LOCK_RQSTS.HIT_E
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.Pq Event 27H , Umask 04H
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RFOs that hit cache lines in E state.
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.It Li L2_STORE_LOCK_RQSTS.HIT_M
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.Pq Event 27H , Umask 08H
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RFOs that hit cache lines in M state.
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.It Li L2_STORE_LOCK_RQSTS.ALL
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.Pq Event 27H , Umask 0FH
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RFOs that access cache lines in any state.
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.It Li L2_L1D_WB_RQSTS.MISS
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.Pq Event 28H , Umask 01H
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Not rejected writebacks from L1D to L2 cache lines
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that missed L2.
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.It Li L2_L1D_WB_RQSTS.HIT_S
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.Pq Event 28H , Umask 02H
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Not rejected writebacks from L1D to L2 cache lines
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in S state.
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.It Li L2_L1D_WB_RQSTS.HIT_E
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.Pq Event 28H , Umask 04H
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Not rejected writebacks from L1D to L2 cache lines
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in E state.
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.It Li L2_L1D_WB_RQSTS.HIT_M
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.Pq Event 28H , Umask 08H
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Not rejected writebacks from L1D to L2 cache lines
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in M state.
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.It Li L2_L1D_WB_RQSTS.ALL
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.Pq Event 28H , Umask 0FH
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Not rejected writebacks from L1D to L2 cache.
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.It Li LONGEST_LAT_CACHE.REFERENCE
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.Pq Event 2EH , Umask 4FH
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This event counts requests originating from the
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core that reference
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a cache line in the last level cache.
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.It Li LONGEST_LAT_CACHE.MISS
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.Pq Event 2EH , Umask 41H
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This event counts each cache miss condition for
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references to the last level cache.
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.It Li CPU_CLK_UNHALTED.THREAD_P
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.Pq Event 3CH , Umask 00H
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Counts the number of thread cycles while the
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thread is not in a halt state. The thread enters
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the halt state when it is running the HLT
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instruction. The core frequency may change from
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time to time due to power or thermal throttling.
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.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
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.Pq Event 3CH , Umask 01H
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Increments at the frequency of XCLK (100 MHz)
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when not halted.
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.It Li L1D_PEND_MISS.PENDING
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.Pq Event 48H , Umask 01H
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Increments the number of outstanding L1D misses
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every cycle.
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Set Cmaks = 1 and Edge =1 to count occurrences.
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.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
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.Pq Event 49H , Umask 01H
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Miss in all TLB levels causes an page walk of
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any page size (4K/2M/4M/1G).
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.It Li DTLB_STORE_MISSES.WALK_COMPLETED
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.Pq Event 49H , Umask 02H
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Miss in all TLB levels causes a page walk that
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completes of any page size (4K/2M/4M/1G).
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.It Li DTLB_STORE_MISSES.WALK_DURATION
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.Pq Event 49H , Umask 04H
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Cycles PMH is busy with this walk.
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.It Li DTLB_STORE_MISSES.STLB_HIT
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.Pq Event 49H , Umask 10H
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Store operations that miss the first TLB level
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but hit the second and do not cause page walks.
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.It Li LOAD_HIT_PRE.SW_PF
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.Pq Event 4CH , Umask 01H
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Not SW-prefetch load dispatches that hit fill
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buffer allocated for S/W prefetch.
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.It Li LOAD_HIT_PER.HW_PF
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.Pq Event 4CH , Umask 02H
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Not SW-prefetch load dispatches that hit fill
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buffer allocated for H/W prefetch.
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.It Li HW_PRE_REQ.DL1_MISS
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.Pq Event 4EH , Umask 02H
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Hardware Prefetch requests that miss the L1D
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cache. A request is being counted each time
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it access the cache & miss it, including if
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a block is applicable or if hit the Fill
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Buffer for example.
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.It Li L1D.REPLACEMENT
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.Pq Event 51H , Umask 01H
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Counts the number of lines brought into the
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L1 data cache.
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.It Li L1D.ALLOCATED_IN_M
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.Pq Event 51H , Umask 02H
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Counts the number of allocations of modified
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L1D cache lines.
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.It Li L1D.EVICTION
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.Pq Event 51H , Umask 04H
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Counts the number of modified lines evicted
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from the L1 data cache due to replacement.
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.It Li L1D.ALL_M_REPLACEMENT
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.Pq Event 51H , Umask 08H
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Cache lines in M state evicted out of L1D due
|
|
to Snoop HitM or dirty line replacement.
|
|
.It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP
|
|
.Pq Event 59H , Umask 0CH
|
|
Increments the number of flags-merge uops in
|
|
flight each cycle.
|
|
Set Cmask = 1 to count cycles.
|
|
.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW
|
|
.Pq Event 59H , Umask 0FH
|
|
Cycles with at least one slow LEA uop allocated.
|
|
.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP
|
|
.Pq Event 59H , Umask 40H
|
|
Number of Multiply packed/scalar single precision
|
|
uops allocated.
|
|
.It Li RESOURCE_STALLS2.ALL_FL_EMPTY
|
|
.Pq Event 5BH , Umask 0CH
|
|
Cycles stalled due to free list empty.
|
|
.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL
|
|
.Pq Event 5BH , Umask 0FH
|
|
Cycles stalled due to control structures full for
|
|
physical registers.
|
|
.It Li RESOURCE_STALLS2.BOB_FULL
|
|
.Pq Event 5BH , Umask 40H
|
|
Cycles Allocator is stalled due Branch Order Buffer.
|
|
.It Li RESOURCE_STALLS2.OOO_RSRC
|
|
.Pq Event 5BH , Umask 4FH
|
|
Cycles stalled due to out of order resources full.
|
|
.It Li CPL_CYCLES.RING0
|
|
.Pq Event 5CH , Umask 01H
|
|
Unhalted core cycles when the thread is in ring 0.
|
|
.It Li CPL_CYCLES.RING123
|
|
.Pq Event 5CH , Umask 02H
|
|
Unhalted core cycles when the thread is not in ring
|
|
0.
|
|
.It Li RS_EVENTS.EMPTY_CYCLES
|
|
.Pq Event 5EH , Umask 01H
|
|
Cycles the RS is empty for the thread.
|
|
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
|
|
.Pq Event 60H , Umask 01H
|
|
Offcore outstanding Demand Data Read
|
|
transactions in SQ to uncore. Set Cmask=1 to count
|
|
cycles.
|
|
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
|
|
.Pq Event 60H , Umask 04H
|
|
Offcore outstanding RFO store transactions in SQ to
|
|
uncore. Set Cmask=1 to count cycles.
|
|
.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
|
|
.Pq Event 60H , Umask 08H
|
|
Offcore outstanding cacheable data read
|
|
transactions in SQ to uncore. Set Cmask=1 to count
|
|
cycles.
|
|
.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
|
|
.Pq Event 63H , Umask 01H
|
|
Cycles in which the L1D and L2 are locked, due to a
|
|
UC lock or split lock.
|
|
.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
|
|
.Pq Event 63H , Umask 02H
|
|
Cycles in which the L1D is locked.
|
|
.It Li IDQ.EMPTY
|
|
.Pq Event 79H , Umask 02H
|
|
Counts cycles the IDQ is empty.
|
|
.It Li IDQ.MITE_UOPS
|
|
.Pq Event 79H , Umask 04H
|
|
Increment each cycle # of uops delivered to IDQ
|
|
from MITE path.
|
|
Set Cmask = 1 to count cycles.
|
|
.It Li IDQ.DSB_UOPS
|
|
.Pq Event 79H , Umask 08H
|
|
Increment each cycle. # of uops delivered to IDQ
|
|
from DSB path.
|
|
Set Cmask = 1 to count cycles.
|
|
.It Li IDQ.MS_DSB_UOPS
|
|
.Pq Event 79H , Umask 10H
|
|
Increment each cycle # of uops delivered to IDQ
|
|
when MS busy by DSB. Set Cmask = 1 to count
|
|
cycles MS is busy. Set Cmask=1 and Edge =1 to
|
|
count MS activations.
|
|
.It Li IDQ.MS_MITE_UOPS
|
|
.Pq Event 79H , Umask 20H
|
|
Increment each cycle # of uops delivered to IDQ
|
|
when MS is busy by MITE. Set Cmask = 1 to count
|
|
cycles.
|
|
.It Li IDQ.MS_UOPS
|
|
.Pq Event 79H , Umask 30H
|
|
Increment each cycle # of uops delivered to IDQ
|
|
from MS by either DSB or MITE. Set Cmask = 1 to
|
|
count cycles.
|
|
.It Li ICACHE.MISSES
|
|
.Pq Event 80H , Umask 02H
|
|
Number of Instruction Cache, Streaming Buffer and
|
|
Victim Cache Misses. Includes UC accesses.
|
|
.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
|
|
.Pq Event 85H , Umask 01H
|
|
Misses in all ITLB levels that cause page walks.
|
|
.It Li ITLB_MISSES.WALK_COMPLETED
|
|
.Pq Event 85H , Umask 02H
|
|
Misses in all ITLB levels that cause completed page
|
|
walks.
|
|
.It Li ITLB_MISSES.WALK_DURATION
|
|
.Pq Event 85H , Umask 04H
|
|
Cycle PMH is busy with a walk.
|
|
.It Li ITLB_MISSES.STLB_HIT
|
|
.Pq Event 85H , Umask 10H
|
|
Number of cache load STLB hits. No page walk.
|
|
.It Li ILD_STALL.LCP
|
|
.Pq Event 87H , Umask 01H
|
|
Stalls caused by changing prefix length of the
|
|
instruction.
|
|
.It Li ILD_STALL.IQ_FULL
|
|
.Pq Event 87H , Umask 04H
|
|
Stall cycles due to IQ is full.
|
|
.It Li BR_INST_EXEC.COND
|
|
.Pq Event 88H , Umask 01H
|
|
Qualify conditional near branch instructions
|
|
executed, but not necessarily retired.
|
|
.It Li BR_INST_EXEC.DIRECT_JMP
|
|
.Pq Event 88H , Umask 02H
|
|
Qualify all unconditional near branch instructions
|
|
excluding calls and indirect branches.
|
|
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
|
|
.Pq Event 88H , Umask 04H
|
|
Qualify executed indirect near branch instructions
|
|
that are not calls nor returns.
|
|
.It Li BR_INST_EXEC.RETURN_NEAR
|
|
.Pq Event 88H , Umask 08H
|
|
Qualify indirect near branches that have a return
|
|
mnemonic.
|
|
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
|
|
.Pq Event 88H , Umask 10H
|
|
Qualify unconditional near call branch instructions,
|
|
excluding non call branch, executed.
|
|
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
|
|
.Pq Event 88H , Umask 20H
|
|
Qualify indirect near calls, including both register
|
|
and memory indirect, executed.
|
|
.It Li BR_INST_EXEC.NONTAKEN
|
|
.Pq Event 88H , Umask 40H
|
|
Qualify non-taken near branches executed.
|
|
.It Li BR_INST_EXEC.TAKEN
|
|
.Pq Event 88H , Umask 80H
|
|
Qualify taken near branches executed. Must
|
|
combine with 01H,02H, 04H, 08H, 10H, 20H.
|
|
.It Li BR_INST_EXE.ALL_BRANCHES
|
|
.Pq Event 88H , Umask FFH
|
|
Counts all near executed branches (not necessarily
|
|
retired).
|
|
.It Li BR_MISP_EXEC.COND
|
|
.Pq Event 89H , Umask 01H
|
|
Qualify conditional near branch instructions
|
|
mispredicted.
|
|
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
|
|
.Pq Event 89H , Umask 04H
|
|
Qualify mispredicted indirect near branch
|
|
instructions that are not calls nor returns.
|
|
.It Li BR_MISP_EXEC.RETURN_NEAR
|
|
.Pq Event 89H , Umask 08H
|
|
Qualify mispredicted indirect near branches that
|
|
have a return mnemonic.
|
|
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
|
|
.Pq Event 89H , Umask 10H
|
|
Qualify mispredicted unconditional near call branch
|
|
instructions, excluding non call branch, executed.
|
|
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
|
|
.Pq Event 89H , Umask 20H
|
|
Qualify mispredicted indirect near calls, including
|
|
both register and memory indirect, executed.
|
|
.It Li BR_MISP_EXEC.NONTAKEN
|
|
.Pq Event 89H , Umask 40H
|
|
Qualify mispredicted non-taken near branches
|
|
executed,.
|
|
.It Li BR_MISP_EXEC.TAKEN
|
|
.Pq Event 89H , Umask 80H
|
|
Qualify mispredicted taken near branches executed.
|
|
Must combine with 01H,02H, 04H, 08H, 10H, 20H
|
|
.It Li BR_MISP_EXEC.ALL_BRANCHES
|
|
.Pq Event 89H , Umask FFH
|
|
Counts all near executed branches (not necessarily
|
|
retired).
|
|
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
|
|
.Pq Event 9CH , Umask 01H
|
|
Count number of non-delivered uops to RAT per
|
|
thread.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_0
|
|
.Pq Event A1H , Umask 01H
|
|
Cycles which a Uop is dispatched on port 0.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_1
|
|
.Pq Event A1H , Umask 02H
|
|
Cycles which a Uop is dispatched on port 1.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_2_LD
|
|
.Pq Event A1H , Umask 04H
|
|
Cycles which a load uop is dispatched on port 2.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_2_STA
|
|
.Pq Event A1H , Umask 08H
|
|
Cycles which a store address uop is dispatched on
|
|
port 2.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_2
|
|
.Pq Event A1H , Umask 0CH
|
|
Cycles which a Uop is dispatched on port 2.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_3_LD
|
|
.Pq Event A1H , Umask 10H
|
|
Cycles which a load uop is dispatched on port 3.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_3_STA
|
|
.Pq Event A1H , Umask 20H
|
|
Cycles which a store address uop is dispatched on
|
|
port 3.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_3
|
|
.Pq Event A1H , Umask 30H
|
|
Cycles which a Uop is dispatched on port 3.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_4
|
|
.Pq Event A1H , Umask 40H
|
|
Cycles which a Uop is dispatched on port 4.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_5
|
|
.Pq Event A1H , Umask 80H
|
|
Cycles which a Uop is dispatched on port 5.
|
|
.It Li RESOURCE_STALLS.ANY
|
|
.Pq Event A2H , Umask 01H
|
|
Cycles Allocation is stalled due to Resource Related
|
|
reason.
|
|
.It Li RESOURCE_STALLS.LB
|
|
.Pq Event A2H , Umask 01H
|
|
Counts the cycles of stall due to lack of load buffers.
|
|
.It Li RESOURCE_STALLS.RS
|
|
.Pq Event A2H , Umask 04H
|
|
Cycles stalled due to no eligible RS entry available.
|
|
.It Li RESOURCE_STALLS.SB
|
|
.Pq Event A2H , Umask 08H
|
|
Cycles stalled due to no store buffers available. (not
|
|
including draining form sync).
|
|
.It Li RESOURCE_STALLS.ROB
|
|
.Pq Event A2H , Umask 10H
|
|
Cycles stalled due to re-order buffer full.
|
|
.It Li RESOURCE_STALLS.FCSW
|
|
.Pq Event A2H , Umask 20H
|
|
Cycles stalled due to writing the FPU control word.
|
|
.It Li RESOURCE_STALLS.MXCSR
|
|
.Pq Event A2H , Umask 40H
|
|
Cycles stalled due to the MXCSR register rename
|
|
occurring to close to a previous MXCSR rename.
|
|
.It Li RESOURCE_STALLS.OTHER
|
|
.Pq Event A2H , Umask 80H
|
|
Cycles stalled while execution was stalled due to
|
|
other resource issues.
|
|
.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
|
|
.Pq Event A3H , Umask 01H
|
|
Cycles with pending L2 miss loads. Set AnyThread
|
|
to count per core.
|
|
.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
|
|
.Pq Event A3H , Umask 02H
|
|
Cycles with pending L1 cache miss loads.Set
|
|
AnyThread to count per core.
|
|
.It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH
|
|
.Pq Event A3H , Umask 04H
|
|
Cycles of dispatch stalls. Set AnyThread to count per
|
|
core.
|
|
.It Li DSB2MITE_SWITCHES.COUNT
|
|
.Pq Event ABH , Umask 01H
|
|
Number of DSB to MITE switches.
|
|
.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES
|
|
.Pq Event ABH , Umask 02H
|
|
Cycles DSB to MITE switches caused delay.
|
|
.It Li DSB_FILL.OTHER_CANCEL
|
|
.Pq Event ACH , Umask 02H
|
|
Cases of cancelling valid DSB fill not because of
|
|
exceeding way limit.
|
|
.It Li DSB_FILL.EXCEED_DSB_LINES
|
|
.Pq Event ACH , Umask 08H
|
|
DSB Fill encountered > 3 DSB lines.
|
|
.It Li DSB_FILL.ALL_CANCEL
|
|
.Pq Event ACH , Umask 0AH
|
|
Cases of cancelling valid Decode Stream Buffer
|
|
(DSB) fill not because of exceeding way limit.
|
|
.It Li ITLB.ITLB_FLUSH
|
|
.Pq Event AEH , Umask 01H
|
|
Counts the number of ITLB flushes, includes
|
|
4k/2M/4M pages.
|
|
.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
|
|
.Pq Event B0H , Umask 01H
|
|
Demand data read requests sent to uncore.
|
|
.It Li OFFCORE_REQUESTS.DEMAND_RFO
|
|
.Pq Event B0H , Umask 04H
|
|
Demand RFO read requests sent to uncore, including
|
|
regular RFOs, locks, ItoM.
|
|
.It Li OFFCORE_REQUESTS.ALL_DATA_RD
|
|
.Pq Event B0H , Umask 08H
|
|
Data read requests sent to uncore (demand and
|
|
prefetch).
|
|
.It Li UOPS_DISPATCHED.THREAD
|
|
.Pq Event B1H , Umask 01H
|
|
Counts total number of uops to be dispatched per-
|
|
thread each cycle. Set Cmask = 1, INV =1 to count
|
|
stall cycles.
|
|
.It Li UOPS_DISPATCHED.CORE
|
|
.Pq Event B1H , Umask 02H
|
|
Counts total number of uops to be dispatched per-
|
|
core each cycle.
|
|
.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL
|
|
.Pq Event B2H , Umask 01H
|
|
Offcore requests buffer cannot take more entries
|
|
for this thread core.
|
|
.It Li AGU_BYPASS_CANCEL.COUNT
|
|
.Pq Event B6H , Umask 01H
|
|
Counts executed load operations with all the
|
|
following traits: 1. addressing of the format [base +
|
|
offset], 2. the offset is between 1 and 2047, 3. the
|
|
address specified in the base register is in one page
|
|
and the address [base+offset] is in another page.
|
|
.It Li OFF_CORE_RESPONSE_0
|
|
.Pq Event B7H , Umask 01H
|
|
(Event B7H, Umask 01H) Off-core Response Performance
|
|
Monitoring; PMC0 only. Requires programming MSR 01A6H
|
|
.It Li OFF_CORE_RESPONSE_1
|
|
.Pq Event BBH , Umask 01H
|
|
(Event BBH, Umask 01H) Off-core Response Performance
|
|
Monitoring; PMC3 only. Requires programming MSR 01A7H
|
|
.It Li TLB_FLUSH.DTLB_THREAD
|
|
.Pq Event BDH , Umask 01H
|
|
DTLB flush attempts of the thread-specific entries.
|
|
.It Li TLB_FLUSH.STLB_ANY
|
|
.Pq Event BDH , Umask 20H
|
|
Count number of STLB flush attempts.
|
|
.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES
|
|
.Pq Event BFH , Umask 05H
|
|
Cycles when dispatched loads are cancelled due to
|
|
L1D bank conflicts with other load ports.
|
|
.It Li INST_RETIRED.ANY_P
|
|
.Pq Event C0H , Umask 00H
|
|
Number of instructions at retirement.
|
|
.It Li INST_RETIRED.ALL
|
|
.Pq Event C0H , Umask 01H
|
|
Precise instruction retired event with HW to reduce
|
|
effect of PEBS shadow in IP distribution.
|
|
.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED
|
|
.Pq Event C1H , Umask 02H
|
|
Instructions that experienced an ITLB miss.
|
|
.It Li OTHER_ASSISTS.AVX_STORE
|
|
.Pq Event C1H , Umask 08H
|
|
Number of assists associated with 256-bit AVX
|
|
store operations.
|
|
.It Li OTHER_ASSISTS.AVX_TO_SSE
|
|
.Pq Event C1H , Umask 10H
|
|
Number of transitions from AVX-256 to legacy SSE
|
|
when penalty applicable.
|
|
.It Li OTHER_ASSISTS.SSE_TO_AVX
|
|
.Pq Event C1H , Umask 20H
|
|
Number of transitions from SSE to AVX-256 when
|
|
penalty applicable.
|
|
.It Li UOPS_RETIRED.ALL
|
|
.Pq Event C2H , Umask 01H
|
|
Counts the number of micro-ops retired, Use
|
|
cmask=1 and invert to count active cycles or stalled
|
|
cycles.
|
|
.It Li UOPS_RETIRED.RETIRE_SLOTS
|
|
.Pq Event C2H , Umask 02H
|
|
Counts the number of retirement slots used each
|
|
cycle.
|
|
.It Li MACHINE_CLEARS.MEMORY_ORDERING
|
|
.Pq Event C3H , Umask 02H
|
|
Counts the number of machine clears due to
|
|
memory order conflicts.
|
|
.It Li MACHINE_CLEARS.SMC
|
|
.Pq Event C3H , Umask 04H
|
|
Counts the number of times that a program writes
|
|
to a code section.
|
|
.It Li MACHINE_CLEARS.MASKMOV
|
|
.Pq Event C3H , Umask 20H
|
|
Counts the number of executed AVX masked load
|
|
operations that refer to an illegal address range
|
|
with the mask bits set to 0.
|
|
.It Li BR_INST_RETIRED.ALL_BRANCH
|
|
.Pq Event C4H , Umask 00H
|
|
Branch instructions at retirement.
|
|
.It Li BR_INST_RETIRED.CONDITIONAL
|
|
.Pq Event C4H , Umask 01H
|
|
Counts the number of conditional branch
|
|
instructions retired.
|
|
.It Li BR_INST_RETIRED.NEAR_CALL
|
|
.Pq Event C4H , Umask 02H
|
|
Direct and indirect near call instructions retired.
|
|
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
|
.Pq Event C4H , Umask 04H
|
|
Counts the number of branch instructions retired.
|
|
.It Li BR_INST_RETIRED.NEAR_RETURN
|
|
.Pq Event C4H , Umask 08H
|
|
Counts the number of near return instructions
|
|
retired.
|
|
.It Li BR_INST_RETIRED.NOT_TAKEN
|
|
.Pq Event C4H , Umask 10H
|
|
Counts the number of not taken branch instructions
|
|
retired.
|
|
.It Li BR_INST_RETIRED.NEAR_TAKEN
|
|
.Pq Event C4H , Umask 20H
|
|
Number of near taken branches retired.
|
|
.It Li BR_INST_RETIRED.FAR_BRANCH
|
|
.Pq Event C4H , Umask 40H
|
|
Number of far branches retired.
|
|
.It Li BR_MISP_RETIRED.ALL_BRANCHES
|
|
.Pq Event C5H , Umask 00H
|
|
Mispredicted branch instructions at retirement.
|
|
.It Li BR_MISP_RETIRED.CONDITIONAL
|
|
.Pq Event C5H , Umask 01H
|
|
Mispredicted conditional branch instructions retired.
|
|
.It Li BR_MISP_RETIRED.NEAR_CALL
|
|
.Pq Event C5H , Umask 02H
|
|
Direct and indirect mispredicted near call
|
|
instructions retired.
|
|
.It Li BR_MISP_RETIRED.ALL_BRANCHES
|
|
.Pq Event C5H , Umask 04H
|
|
Mispredicted macro branch instructions retired.
|
|
.It Li BR_MISP_RETIRED.NOT_TAKEN
|
|
.Pq Event C5H , Umask 10H
|
|
Mispredicted not taken branch instructions retired.
|
|
.It Li BR_MISP_RETIRED.TAKEN
|
|
.Pq Event C5H , Umask 20H
|
|
Mispredicted taken branch instructions retired.
|
|
.It Li FP_ASSIST.X87_OUTPUT
|
|
.Pq Event CAH , Umask 02H
|
|
Number of X87 assists due to output value.
|
|
.It Li FP_ASSIST.X87_INPUT
|
|
.Pq Event CAH , Umask 04H
|
|
Number of X87 assists due to input value.
|
|
.It Li FP_ASSIST.SIMD_OUTPUT
|
|
.Pq Event CAH , Umask 08H
|
|
Number of SIMD FP assists due to output values.
|
|
.It Li FP_ASSIST.SIMD_INPUT
|
|
.Pq Event CAH , Umask 10H
|
|
Number of SIMD FP assists due to input values.
|
|
.It Li FP_ASSIST.ANY 1EH
|
|
.Pq Event CAH , Umask
|
|
Cycles with any input/output SSE* or FP assists.
|
|
.It Li ROB_MISC_EVENTS.LBR_INSERTS
|
|
.Pq Event CCH , Umask 20H
|
|
Count cases of saving new LBR records by
|
|
hardware.
|
|
.It Li MEM_TRANS_RETIRED.LOAD_LATENCY
|
|
.Pq Event CDH , Umask 01H
|
|
Sample loads with specified latency threshold.
|
|
PMC3 only.
|
|
.It Li MEM_TRANS_RETIRED.PRECISE_STORE
|
|
.Pq Event CDH , Umask 02H
|
|
Sample stores and collect precise store operation
|
|
via PEBS record. PMC3 only.
|
|
.It Li MEM_UOP_RETIRED.LOADS
|
|
.Pq Event D0H , Umask 10H
|
|
Qualify retired memory uops that are loads.
|
|
Combine with umask 10H, 20H, 40H, 80H.
|
|
.It Li MEM_UOP_RETIRED.STORES
|
|
.Pq Event D0H , Umask 02H
|
|
Qualify retired memory uops that are stores.
|
|
Combine with umask 10H, 20H, 40H, 80H.
|
|
.It Li MEM_UOP_RETIRED.STLB_MISS
|
|
.Pq Event D0H , Umask
|
|
Qualify retired memory uops with STLB miss. Must
|
|
combine with umask 01H, 02H, to produce counts.
|
|
.It Li MEM_UOP_RETIRED.LOCK
|
|
.Pq Event D0H , Umask
|
|
Qualify retired memory uops with lock. Must
|
|
combine with umask 01H, 02H, to produce counts.
|
|
.It Li MEM_UOP_RETIRED.SPLIT
|
|
.Pq Event D0H , Umask
|
|
Qualify retired memory uops with line split. Must
|
|
combine with umask 01H, 02H, to produce counts.
|
|
.It Li MEM_UOP_RETIRED_ALL
|
|
.Pq Event D0H , Umask
|
|
Qualify any retired memory uops. Must combine
|
|
with umask 01H, 02H, to produce counts.
|
|
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
|
.Pq Event D1H , Umask 01H
|
|
Retired load uops with L1 cache hits as data
|
|
sources.
|
|
.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
|
|
.Pq Event D1H , Umask 02H
|
|
Retired load uops with L2 cache hits as data
|
|
sources.
|
|
.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
|
|
.Pq Event D1H , Umask 04H
|
|
Retired load uops which data sources were data hits
|
|
in LLC without snoops required.
|
|
.It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS
|
|
.Pq Event D1H , Umask 20H
|
|
Retired load uops which data sources were data
|
|
missed LLC (excluding unknown data source).
|
|
.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
|
|
.Pq Event D1H , Umask 40H
|
|
Retired load uops which data sources were load
|
|
uops missed L1 but hit FB due to preceding miss to
|
|
the same cache line with data not ready.
|
|
.It Li MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS
|
|
.Pq Event D4H , Umask 02H
|
|
Retired load uops with unknown information as data
|
|
source in cache serviced the load.
|
|
.It Li BACLEARS.ANY
|
|
.Pq Event E6H , Umask 01H
|
|
Counts the number of times the front end is re-
|
|
steered, mainly when the BPU cannot provide a
|
|
correct prediction and this is corrected by other
|
|
branch handling mechanisms at the front end.
|
|
.It Li L2_TRANS.DEMAND_DATA_RD
|
|
.Pq Event F0H , Umask 01H
|
|
Demand Data Read requests that access L2 cache.
|
|
.It Li L2_TRANS.RFO
|
|
.Pq Event F0H , Umask 02H
|
|
RFO requests that access L2 cache.
|
|
.It Li L2_TRANS.CODE_RD
|
|
.Pq Event F0H , Umask 04H
|
|
L2 cache accesses when fetching instructions.
|
|
.It Li L2_TRANS.ALL_PF
|
|
.Pq Event F0H , Umask 08H
|
|
L2 or LLC HW prefetches that access L2 cache.
|
|
.It Li L2_TRANS.L1D_WB
|
|
.Pq Event F0H , Umask 10H
|
|
L1D writebacks that access L2 cache.
|
|
.It Li L2_TRANS.L2_FILL
|
|
.Pq Event F0H , Umask 20H
|
|
L2 fill requests that access L2 cache.
|
|
.It Li L2_TRANS.L2_WB
|
|
.Pq Event F0H , Umask 40H
|
|
L2 writebacks that access L2 cache.
|
|
.It Li L2_TRANS.ALL_REQUESTS
|
|
.Pq Event F0H , Umask 80H
|
|
Transactions accessing L2 pipe.
|
|
.It Li L2_LINES_IN.I
|
|
.Pq Event F1H , Umask 01H
|
|
L2 cache lines in I state filling L2.
|
|
.It Li L2_LINES_IN.S
|
|
.Pq Event F1H , Umask 02H
|
|
L2 cache lines in S state filling L2.
|
|
.It Li L2_LINES_IN.E
|
|
.Pq Event F1H , Umask 04H
|
|
L2 cache lines in E state filling L2.
|
|
.It Li L2_LINES-IN.ALL
|
|
.Pq Event F1H , Umask 07H
|
|
L2 cache lines filling L2.
|
|
.It Li L2_LINES_OUT.DEMAND_CLEAN
|
|
.Pq Event F2H , Umask 01H
|
|
Clean L2 cache lines evicted by demand.
|
|
.It Li L2_LINES_OUT.DEMAND_DIRTY
|
|
.Pq Event F2H , Umask 02H
|
|
Dirty L2 cache lines evicted by demand.
|
|
.It Li L2_LINES_OUT.PF_CLEAN
|
|
.Pq Event F2H , Umask 04H
|
|
Clean L2 cache lines evicted by L2 prefetch.
|
|
.It Li L2_LINES_OUT.PF_DIRTY
|
|
.Pq Event F2H , Umask 08H
|
|
Dirty L2 cache lines evicted by L2 prefetch.
|
|
.It Li L2_LINES_OUT.DIRTY_ALL
|
|
.Pq Event F2H , Umask 0AH
|
|
Dirty L2 cache lines filling the L2.
|
|
.It Li SQ_MISC.SPLIT_LOCK
|
|
.Pq Event F4H , Umask 10H
|
|
Split locks in SQ.
|
|
.El
|
|
.Sh SEE ALSO
|
|
.Xr pmc 3 ,
|
|
.Xr pmc.atom 3 ,
|
|
.Xr pmc.core 3 ,
|
|
.Xr pmc.iaf 3 ,
|
|
.Xr pmc.ucf 3 ,
|
|
.Xr pmc.k7 3 ,
|
|
.Xr pmc.k8 3 ,
|
|
.Xr pmc.p4 3 ,
|
|
.Xr pmc.p5 3 ,
|
|
.Xr pmc.p6 3 ,
|
|
.Xr pmc.corei7 3 ,
|
|
.Xr pmc.corei7uc 3 ,
|
|
.Xr pmc.ivybridge 3 ,
|
|
.Xr pmc.ivybridgexeon 3 ,
|
|
.Xr pmc.sandybridge 3 ,
|
|
.Xr pmc.sandybridgeuc 3 ,
|
|
.Xr pmc.westmere 3 ,
|
|
.Xr pmc.westmereuc 3 ,
|
|
.Xr pmc.soft 3 ,
|
|
.Xr pmc.tsc 3 ,
|
|
.Xr pmc_cpuinfo 3 ,
|
|
.Xr pmclog 3 ,
|
|
.Xr hwpmc 4
|
|
.Sh HISTORY
|
|
The
|
|
.Nm pmc
|
|
library first appeared in
|
|
.Fx 6.0 .
|
|
.Sh AUTHORS
|
|
.An -nosplit
|
|
The
|
|
.Lb libpmc
|
|
library was written by
|
|
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
|
|
The support for the Sandy Bridge Xeon
|
|
microarchitecture was written by
|
|
.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com .
|