b803d0b790
from SiFive, Inc. The first core on this SoC (hart 0) is a 64-bit microcontroller. o Pick a hart to run boot process using hart lottery. This allows to exclude hart 0 from running the boot process. (BBL releases hart 0 after the main harts, so it never wins the lottery). o Renumber CPUs early on boot. Exclude non-MMU cores. Store the original hart ID in struct pcpu. This allows to find out the correct destination for IPIs and remote sfence calls. Thanks to SiFive, Inc for the board provided. Reviewed by: markj Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D20225
89 lines
2.9 KiB
C
89 lines
2.9 KiB
C
/*-
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* Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org>
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* Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: FreeBSD: src/sys/i386/include/globaldata.h,v 1.27 2001/04/27
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PCPU_H_
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#define _MACHINE_PCPU_H_
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#define ALT_STACK_SIZE 128
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#define PCPU_MD_FIELDS \
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struct pmap *pc_curpmap; /* Currently active pmap */ \
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uint32_t pc_pending_ipis; /* IPIs pending to this CPU */ \
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uint32_t pc_hart; /* Hart ID */ \
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char __pad[57]
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#ifdef _KERNEL
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struct pcb;
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struct pcpu;
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static inline struct pcpu *
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get_pcpu(void)
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{
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struct pcpu *pcpu;
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__asm __volatile("mv %0, gp" : "=&r"(pcpu));
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return (pcpu);
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}
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static inline struct thread *
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get_curthread(void)
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{
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struct thread *td;
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__asm __volatile("ld %0, 0(gp)" : "=&r"(td));
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return (td);
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}
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#define curthread get_curthread()
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#define PCPU_GET(member) (get_pcpu()->pc_ ## member)
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#define PCPU_ADD(member, value) (get_pcpu()->pc_ ## member += (value))
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#define PCPU_INC(member) PCPU_ADD(member, 1)
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#define PCPU_PTR(member) (&get_pcpu()->pc_ ## member)
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#define PCPU_SET(member,value) (get_pcpu()->pc_ ## member = (value))
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#endif /* _KERNEL */
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#endif /* !_MACHINE_PCPU_H_ */
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