808 lines
17 KiB
C
808 lines
17 KiB
C
/*-
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* Copyright (c) 2010, George V. Neville-Neil <gnn@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_hwpmc_hooks.h"
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#include <sys/param.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <sys/systm.h>
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#include <machine/pmc_mdep.h>
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#include <machine/md_var.h>
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#include <machine/mips_opcode.h>
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#include <machine/vmparam.h>
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int mips_npmcs;
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/*
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* Per-processor information.
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*/
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struct mips_cpu {
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struct pmc_hw *pc_mipspmcs;
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};
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static struct mips_cpu **mips_pcpu;
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#if defined(__mips_n64)
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# define MIPS_IS_VALID_KERNELADDR(reg) ((((reg) & 3) == 0) && \
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((vm_offset_t)(reg) >= MIPS_XKPHYS_START))
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#else
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# define MIPS_IS_VALID_KERNELADDR(reg) ((((reg) & 3) == 0) && \
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((vm_offset_t)(reg) >= MIPS_KSEG0_START))
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#endif
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/*
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* We need some reasonable default to prevent backtrace code
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* from wandering too far
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*/
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#define MAX_FUNCTION_SIZE 0x10000
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#define MAX_PROLOGUE_SIZE 0x100
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static int
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mips_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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enum pmc_event pe;
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uint32_t caps, config, counter;
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uint32_t event;
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int i;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[mips,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < mips_npmcs,
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("[mips,%d] illegal row index %d", __LINE__, ri));
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caps = a->pm_caps;
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if (a->pm_class != mips_pmc_spec.ps_cpuclass)
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return (EINVAL);
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pe = a->pm_ev;
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counter = MIPS_CTR_ALL;
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event = 0;
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for (i = 0; i < mips_event_codes_size; i++) {
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if (mips_event_codes[i].pe_ev == pe) {
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event = mips_event_codes[i].pe_code;
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counter = mips_event_codes[i].pe_counter;
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break;
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}
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}
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if (i == mips_event_codes_size)
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return (EINVAL);
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if ((counter != MIPS_CTR_ALL) && (counter != ri))
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return (EINVAL);
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config = mips_get_perfctl(cpu, ri, event, caps);
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pm->pm_md.pm_mips_evsel = config;
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PMCDBG2(MDP,ALL,2,"mips-allocate ri=%d -> config=0x%x", ri, config);
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return 0;
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}
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static int
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mips_read_pmc(int cpu, int ri, pmc_value_t *v)
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{
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struct pmc *pm;
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pmc_value_t tmp;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[mips,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < mips_npmcs,
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("[mips,%d] illegal row index %d", __LINE__, ri));
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pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
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tmp = mips_pmcn_read(ri);
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PMCDBG2(MDP,REA,2,"mips-read id=%d -> %jd", ri, tmp);
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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*v = tmp - (1UL << (mips_pmc_spec.ps_counter_width - 1));
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else
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*v = tmp;
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return 0;
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}
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static int
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mips_write_pmc(int cpu, int ri, pmc_value_t v)
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{
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struct pmc *pm;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[mips,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < mips_npmcs,
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("[mips,%d] illegal row-index %d", __LINE__, ri));
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pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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v = (1UL << (mips_pmc_spec.ps_counter_width - 1)) - v;
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PMCDBG3(MDP,WRI,1,"mips-write cpu=%d ri=%d v=%jx", cpu, ri, v);
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mips_pmcn_write(ri, v);
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return 0;
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}
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static int
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mips_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct pmc_hw *phw;
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PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[mips,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < mips_npmcs,
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("[mips,%d] illegal row-index %d", __LINE__, ri));
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phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
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KASSERT(pm == NULL || phw->phw_pmc == NULL,
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("[mips,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
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__LINE__, pm, phw->phw_pmc));
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phw->phw_pmc = pm;
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return 0;
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}
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static int
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mips_start_pmc(int cpu, int ri)
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{
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uint32_t config;
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struct pmc *pm;
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struct pmc_hw *phw;
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phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
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pm = phw->phw_pmc;
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config = pm->pm_md.pm_mips_evsel;
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/* Enable the PMC. */
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switch (ri) {
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case 0:
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mips_wr_perfcnt0(config);
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break;
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case 1:
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mips_wr_perfcnt2(config);
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break;
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default:
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break;
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}
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return 0;
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}
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static int
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mips_stop_pmc(int cpu, int ri)
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{
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struct pmc *pm;
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struct pmc_hw *phw;
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phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
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pm = phw->phw_pmc;
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/*
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* Disable the PMCs.
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*
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* Clearing the entire register turns the counter off as well
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* as removes the previously sampled event.
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*/
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switch (ri) {
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case 0:
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mips_wr_perfcnt0(0);
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break;
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case 1:
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mips_wr_perfcnt2(0);
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break;
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default:
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break;
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}
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return 0;
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}
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static int
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mips_release_pmc(int cpu, int ri, struct pmc *pmc)
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{
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struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[mips,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < mips_npmcs,
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("[mips,%d] illegal row-index %d", __LINE__, ri));
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phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
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KASSERT(phw->phw_pmc == NULL,
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("[mips,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
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return 0;
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}
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static int
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mips_pmc_intr(int cpu, struct trapframe *tf)
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{
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int error;
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int retval, ri;
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struct pmc *pm;
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struct mips_cpu *pc;
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uint32_t r0, r2;
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pmc_value_t r;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[mips,%d] CPU %d out of range", __LINE__, cpu));
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retval = 0;
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pc = mips_pcpu[cpu];
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/* Stop PMCs without clearing the counter */
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r0 = mips_rd_perfcnt0();
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mips_wr_perfcnt0(r0 & ~(0x1f));
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r2 = mips_rd_perfcnt2();
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mips_wr_perfcnt2(r2 & ~(0x1f));
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for (ri = 0; ri < mips_npmcs; ri++) {
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pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
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if (pm == NULL)
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continue;
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if (! PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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continue;
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r = mips_pmcn_read(ri);
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/* If bit 31 is set, the counter has overflowed */
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if ((r & (1UL << (mips_pmc_spec.ps_counter_width - 1))) == 0)
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continue;
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retval = 1;
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if (pm->pm_state != PMC_STATE_RUNNING)
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continue;
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error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
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TRAPF_USERMODE(tf));
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if (error) {
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/* Clear/disable the relevant counter */
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if (ri == 0)
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r0 = 0;
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else if (ri == 1)
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r2 = 0;
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mips_stop_pmc(cpu, ri);
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}
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/* Reload sampling count */
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mips_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
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}
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/*
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* Re-enable the PMC counters where they left off.
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*
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* Any counter which overflowed will have its sample count
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* reloaded in the loop above.
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*/
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mips_wr_perfcnt0(r0);
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mips_wr_perfcnt2(r2);
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return retval;
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}
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static int
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mips_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
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{
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int error;
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struct pmc_hw *phw;
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char mips_name[PMC_NAME_MAX];
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[mips,%d], illegal CPU %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < mips_npmcs,
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("[mips,%d] row-index %d out of range", __LINE__, ri));
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phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
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snprintf(mips_name, sizeof(mips_name), "MIPS-%d", ri);
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if ((error = copystr(mips_name, pi->pm_name, PMC_NAME_MAX,
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NULL)) != 0)
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return error;
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pi->pm_class = mips_pmc_spec.ps_cpuclass;
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if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
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pi->pm_enabled = TRUE;
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*ppmc = phw->phw_pmc;
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} else {
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pi->pm_enabled = FALSE;
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*ppmc = NULL;
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}
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return (0);
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}
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static int
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mips_get_config(int cpu, int ri, struct pmc **ppm)
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{
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*ppm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
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return 0;
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}
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/*
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* XXX don't know what we should do here.
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*/
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static int
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mips_pmc_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
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{
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return 0;
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}
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static int
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mips_pmc_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
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{
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return 0;
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}
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static int
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mips_pcpu_init(struct pmc_mdep *md, int cpu)
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{
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int first_ri, i;
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struct pmc_cpu *pc;
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struct mips_cpu *pac;
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struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[mips,%d] wrong cpu number %d", __LINE__, cpu));
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PMCDBG1(MDP,INI,1,"mips-init cpu=%d", cpu);
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mips_pcpu[cpu] = pac = malloc(sizeof(struct mips_cpu), M_PMC,
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M_WAITOK|M_ZERO);
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pac->pc_mipspmcs = malloc(sizeof(struct pmc_hw) * mips_npmcs,
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M_PMC, M_WAITOK|M_ZERO);
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pc = pmc_pcpu[cpu];
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first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS].pcd_ri;
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KASSERT(pc != NULL, ("[mips,%d] NULL per-cpu pointer", __LINE__));
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for (i = 0, phw = pac->pc_mipspmcs; i < mips_npmcs; i++, phw++) {
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phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
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PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
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phw->phw_pmc = NULL;
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pc->pc_hwpmcs[i + first_ri] = phw;
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}
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/*
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* Clear the counter control register which has the effect
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* of disabling counting.
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*/
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for (i = 0; i < mips_npmcs; i++)
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mips_pmcn_write(i, 0);
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return 0;
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}
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static int
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mips_pcpu_fini(struct pmc_mdep *md, int cpu)
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{
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return 0;
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}
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struct pmc_mdep *
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pmc_mips_initialize()
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{
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struct pmc_mdep *pmc_mdep;
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struct pmc_classdep *pcd;
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/*
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* TODO: Use More bit of PerfCntlX register to detect actual
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* number of counters
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*/
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mips_npmcs = 2;
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PMCDBG1(MDP,INI,1,"mips-init npmcs=%d", mips_npmcs);
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/*
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* Allocate space for pointers to PMC HW descriptors and for
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* the MDEP structure used by MI code.
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*/
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mips_pcpu = malloc(sizeof(struct mips_cpu *) * pmc_cpu_max(), M_PMC,
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M_WAITOK|M_ZERO);
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/* Just one class */
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pmc_mdep = pmc_mdep_alloc(1);
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pmc_mdep->pmd_cputype = mips_pmc_spec.ps_cputype;
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pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS];
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pcd->pcd_caps = mips_pmc_spec.ps_capabilities;
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pcd->pcd_class = mips_pmc_spec.ps_cpuclass;
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pcd->pcd_num = mips_npmcs;
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pcd->pcd_ri = pmc_mdep->pmd_npmc;
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pcd->pcd_width = mips_pmc_spec.ps_counter_width;
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pcd->pcd_allocate_pmc = mips_allocate_pmc;
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pcd->pcd_config_pmc = mips_config_pmc;
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pcd->pcd_pcpu_fini = mips_pcpu_fini;
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pcd->pcd_pcpu_init = mips_pcpu_init;
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pcd->pcd_describe = mips_describe;
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pcd->pcd_get_config = mips_get_config;
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pcd->pcd_read_pmc = mips_read_pmc;
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pcd->pcd_release_pmc = mips_release_pmc;
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pcd->pcd_start_pmc = mips_start_pmc;
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pcd->pcd_stop_pmc = mips_stop_pmc;
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pcd->pcd_write_pmc = mips_write_pmc;
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pmc_mdep->pmd_intr = mips_pmc_intr;
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pmc_mdep->pmd_switch_in = mips_pmc_switch_in;
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pmc_mdep->pmd_switch_out = mips_pmc_switch_out;
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pmc_mdep->pmd_npmc += mips_npmcs;
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return (pmc_mdep);
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}
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void
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pmc_mips_finalize(struct pmc_mdep *md)
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{
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(void) md;
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}
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#ifdef HWPMC_MIPS_BACKTRACE
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static int
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pmc_next_frame(register_t *pc, register_t *sp)
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{
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InstFmt i;
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uintptr_t va;
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uint32_t instr, mask;
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int more, stksize;
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register_t ra = 0;
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/* Jump here after a nonstandard (interrupt handler) frame */
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stksize = 0;
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/* check for bad SP: could foul up next frame */
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if (!MIPS_IS_VALID_KERNELADDR(*sp)) {
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goto error;
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}
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/* check for bad PC */
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if (!MIPS_IS_VALID_KERNELADDR(*pc)) {
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goto error;
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}
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/*
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* Find the beginning of the current subroutine by scanning
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* backwards from the current PC for the end of the previous
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* subroutine.
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*/
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va = *pc - sizeof(int);
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while (1) {
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instr = *((uint32_t *)va);
|
|
|
|
/* [d]addiu sp,sp,-X */
|
|
if (((instr & 0xffff8000) == 0x27bd8000)
|
|
|| ((instr & 0xffff8000) == 0x67bd8000))
|
|
break;
|
|
|
|
/* jr ra */
|
|
if (instr == 0x03e00008) {
|
|
/* skip over branch-delay slot instruction */
|
|
va += 2 * sizeof(int);
|
|
break;
|
|
}
|
|
|
|
va -= sizeof(int);
|
|
}
|
|
|
|
/* skip over nulls which might separate .o files */
|
|
while ((instr = *((uint32_t *)va)) == 0)
|
|
va += sizeof(int);
|
|
|
|
/* scan forwards to find stack size and any saved registers */
|
|
stksize = 0;
|
|
more = 3;
|
|
mask = 0;
|
|
for (; more; va += sizeof(int),
|
|
more = (more == 3) ? 3 : more - 1) {
|
|
/* stop if hit our current position */
|
|
if (va >= *pc)
|
|
break;
|
|
instr = *((uint32_t *)va);
|
|
i.word = instr;
|
|
switch (i.JType.op) {
|
|
case OP_SPECIAL:
|
|
switch (i.RType.func) {
|
|
case OP_JR:
|
|
case OP_JALR:
|
|
more = 2; /* stop after next instruction */
|
|
break;
|
|
|
|
case OP_SYSCALL:
|
|
case OP_BREAK:
|
|
more = 1; /* stop now */
|
|
}
|
|
break;
|
|
|
|
case OP_BCOND:
|
|
case OP_J:
|
|
case OP_JAL:
|
|
case OP_BEQ:
|
|
case OP_BNE:
|
|
case OP_BLEZ:
|
|
case OP_BGTZ:
|
|
more = 2; /* stop after next instruction */
|
|
break;
|
|
|
|
case OP_COP0:
|
|
case OP_COP1:
|
|
case OP_COP2:
|
|
case OP_COP3:
|
|
switch (i.RType.rs) {
|
|
case OP_BCx:
|
|
case OP_BCy:
|
|
more = 2; /* stop after next instruction */
|
|
}
|
|
break;
|
|
|
|
case OP_SW:
|
|
case OP_SD:
|
|
/*
|
|
* SP is being saved using S8(FP). Most likely it indicates
|
|
* that SP is modified in the function and we can't get
|
|
* its value safely without emulating code backward
|
|
* So just bail out on functions like this
|
|
*/
|
|
if ((i.IType.rs == 30) && (i.IType.rt = 29))
|
|
return (-1);
|
|
|
|
/* look for saved registers on the stack */
|
|
if (i.IType.rs != 29)
|
|
break;
|
|
/* only restore the first one */
|
|
if (mask & (1 << i.IType.rt))
|
|
break;
|
|
mask |= (1 << i.IType.rt);
|
|
if (i.IType.rt == 31)
|
|
ra = *((register_t *)(*sp + (short)i.IType.imm));
|
|
break;
|
|
|
|
case OP_ADDI:
|
|
case OP_ADDIU:
|
|
case OP_DADDI:
|
|
case OP_DADDIU:
|
|
/* look for stack pointer adjustment */
|
|
if (i.IType.rs != 29 || i.IType.rt != 29)
|
|
break;
|
|
stksize = -((short)i.IType.imm);
|
|
}
|
|
}
|
|
|
|
if (!MIPS_IS_VALID_KERNELADDR(ra))
|
|
return (-1);
|
|
|
|
*pc = ra;
|
|
*sp += stksize;
|
|
|
|
return (0);
|
|
|
|
error:
|
|
return (-1);
|
|
}
|
|
|
|
static int
|
|
pmc_next_uframe(register_t *pc, register_t *sp, register_t *ra)
|
|
{
|
|
int offset, registers_on_stack;
|
|
uint32_t opcode, mask;
|
|
register_t function_start;
|
|
int stksize;
|
|
InstFmt i;
|
|
|
|
registers_on_stack = 0;
|
|
mask = 0;
|
|
function_start = 0;
|
|
offset = 0;
|
|
stksize = 0;
|
|
|
|
while (offset < MAX_FUNCTION_SIZE) {
|
|
opcode = fuword32((void *)(*pc - offset));
|
|
|
|
/* [d]addiu sp, sp, -X*/
|
|
if (((opcode & 0xffff8000) == 0x27bd8000)
|
|
|| ((opcode & 0xffff8000) == 0x67bd8000)) {
|
|
function_start = *pc - offset;
|
|
registers_on_stack = 1;
|
|
break;
|
|
}
|
|
|
|
/* lui gp, X */
|
|
if ((opcode & 0xffff8000) == 0x3c1c0000) {
|
|
/*
|
|
* Function might start with this instruction
|
|
* Keep an eye on "jr ra" and sp correction
|
|
* with positive value further on
|
|
*/
|
|
function_start = *pc - offset;
|
|
}
|
|
|
|
if (function_start) {
|
|
/*
|
|
* Stop looking further. Possible end of
|
|
* function instruction: it means there is no
|
|
* stack modifications, sp is unchanged
|
|
*/
|
|
|
|
/* [d]addiu sp,sp,X */
|
|
if (((opcode & 0xffff8000) == 0x27bd0000)
|
|
|| ((opcode & 0xffff8000) == 0x67bd0000))
|
|
break;
|
|
|
|
if (opcode == 0x03e00008)
|
|
break;
|
|
}
|
|
|
|
offset += sizeof(int);
|
|
}
|
|
|
|
if (!function_start)
|
|
return (-1);
|
|
|
|
if (registers_on_stack) {
|
|
offset = 0;
|
|
while ((offset < MAX_PROLOGUE_SIZE)
|
|
&& ((function_start + offset) < *pc)) {
|
|
i.word = fuword32((void *)(function_start + offset));
|
|
switch (i.JType.op) {
|
|
case OP_SW:
|
|
/* look for saved registers on the stack */
|
|
if (i.IType.rs != 29)
|
|
break;
|
|
/* only restore the first one */
|
|
if (mask & (1 << i.IType.rt))
|
|
break;
|
|
mask |= (1 << i.IType.rt);
|
|
if (i.IType.rt == 31)
|
|
*ra = fuword32((void *)(*sp + (short)i.IType.imm));
|
|
break;
|
|
|
|
#if defined(__mips_n64)
|
|
case OP_SD:
|
|
/* look for saved registers on the stack */
|
|
if (i.IType.rs != 29)
|
|
break;
|
|
/* only restore the first one */
|
|
if (mask & (1 << i.IType.rt))
|
|
break;
|
|
mask |= (1 << i.IType.rt);
|
|
/* ra */
|
|
if (i.IType.rt == 31)
|
|
*ra = fuword64((void *)(*sp + (short)i.IType.imm));
|
|
break;
|
|
#endif
|
|
|
|
case OP_ADDI:
|
|
case OP_ADDIU:
|
|
case OP_DADDI:
|
|
case OP_DADDIU:
|
|
/* look for stack pointer adjustment */
|
|
if (i.IType.rs != 29 || i.IType.rt != 29)
|
|
break;
|
|
stksize = -((short)i.IType.imm);
|
|
}
|
|
|
|
offset += sizeof(int);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* We reached the end of backtrace
|
|
*/
|
|
if (*pc == *ra)
|
|
return (-1);
|
|
|
|
*pc = *ra;
|
|
*sp += stksize;
|
|
|
|
return (0);
|
|
}
|
|
|
|
#endif /* HWPMC_MIPS_BACKTRACE */
|
|
|
|
struct pmc_mdep *
|
|
pmc_md_initialize()
|
|
{
|
|
return pmc_mips_initialize();
|
|
}
|
|
|
|
void
|
|
pmc_md_finalize(struct pmc_mdep *md)
|
|
{
|
|
return pmc_mips_finalize(md);
|
|
}
|
|
|
|
int
|
|
pmc_save_kernel_callchain(uintptr_t *cc, int nframes,
|
|
struct trapframe *tf)
|
|
{
|
|
register_t pc, ra, sp;
|
|
int frames = 0;
|
|
|
|
pc = tf->pc;
|
|
sp = tf->sp;
|
|
ra = tf->ra;
|
|
|
|
cc[frames++] = pc;
|
|
|
|
#ifdef HWPMC_MIPS_BACKTRACE
|
|
/*
|
|
* Unwind, and unwind, and unwind
|
|
*/
|
|
while (1) {
|
|
if (frames >= nframes)
|
|
break;
|
|
|
|
if (pmc_next_frame(&pc, &sp) < 0)
|
|
break;
|
|
|
|
cc[frames++] = pc;
|
|
}
|
|
#endif
|
|
|
|
return (frames);
|
|
}
|
|
|
|
int
|
|
pmc_save_user_callchain(uintptr_t *cc, int nframes,
|
|
struct trapframe *tf)
|
|
{
|
|
register_t pc, ra, sp;
|
|
int frames = 0;
|
|
|
|
pc = tf->pc;
|
|
sp = tf->sp;
|
|
ra = tf->ra;
|
|
|
|
cc[frames++] = pc;
|
|
|
|
#ifdef HWPMC_MIPS_BACKTRACE
|
|
|
|
/*
|
|
* Unwind, and unwind, and unwind
|
|
*/
|
|
while (1) {
|
|
if (frames >= nframes)
|
|
break;
|
|
|
|
if (pmc_next_uframe(&pc, &sp, &ra) < 0)
|
|
break;
|
|
|
|
cc[frames++] = pc;
|
|
}
|
|
#endif
|
|
|
|
return (frames);
|
|
}
|