b8b0747b3c
console so initialized will work upon return from cninit. While this is the very next line, other platforms setup all this stuff before calling cninit. Also, initialize the SDRAM base register in the inner block in at91_ramsize().
451 lines
14 KiB
C
451 lines
14 KiB
C
/*-
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* machdep.c
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*
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* Machine dependant functions for kernel setup
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*
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* This file needs a lot of work.
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*
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* Created : 17/09/94
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysproto.h>
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#include <sys/signalvar.h>
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#include <sys/imgact.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/linker.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/ptrace.h>
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#include <sys/cons.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/buf.h>
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#include <sys/exec.h>
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#include <sys/kdb.h>
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#include <sys/msgbuf.h>
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#include <machine/reg.h>
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#include <machine/cpu.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <vm/vm_pager.h>
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#include <vm/vm_map.h>
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#include <machine/pmap.h>
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#include <machine/vmparam.h>
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#include <machine/pcb.h>
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#include <machine/undefined.h>
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#include <machine/machdep.h>
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#include <machine/metadata.h>
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#include <machine/armreg.h>
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#include <machine/bus.h>
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#include <sys/reboot.h>
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#include <arm/at91/at91board.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91sam9g20reg.h>
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#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
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#define KERNEL_PT_KERN 1
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#define KERNEL_PT_KERN_NUM 22
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#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */
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#define KERNEL_PT_AFKERNEL_NUM 5
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/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
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#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
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/* Define various stack sizes in pages */
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#define IRQ_STACK_SIZE 1
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#define ABT_STACK_SIZE 1
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#define UND_STACK_SIZE 1
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extern u_int data_abort_handler_address;
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extern u_int prefetch_abort_handler_address;
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extern u_int undefined_handler_address;
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struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
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extern void *_end;
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extern int *end;
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struct pcpu __pcpu;
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struct pcpu *pcpup = &__pcpu;
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/* Physical and virtual addresses for some global pages */
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vm_paddr_t phys_avail[10];
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vm_paddr_t dump_avail[4];
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vm_offset_t physical_pages;
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struct pv_addr systempage;
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struct pv_addr msgbufpv;
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struct pv_addr irqstack;
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struct pv_addr undstack;
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struct pv_addr abtstack;
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struct pv_addr kernelstack;
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static void *boot_arg1;
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static void *boot_arg2;
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static struct trapframe proc0_tf;
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/* Static device mappings. */
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const struct pmap_devmap at91_devmap[] = {
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/*
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* Map the on-board devices VA == PA so that we can access them
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* with the MMU on or off.
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*/
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{
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/*
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* This at least maps the interrupt controller, the UART
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* and the timer. Other devices should use newbus to
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* map their memory anyway.
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*/
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0xdff00000,
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0xfff00000,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/* We can't just map the OHCI registers VA == PA, because
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* AT91xx_xxx_BASE belongs to the userland address space.
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* We could just choose a different virtual address, but a better
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* solution would probably be to just use pmap_mapdev() to allocate
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* KVA, as we don't need the OHCI controller before the vm
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* initialization is done. However, the AT91 resource allocation
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* system doesn't know how to use pmap_mapdev() yet.
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* Care must be taken to ensure PA and VM address do not overlap
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* between entries.
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*/
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{
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/*
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* Add the ohci controller, and anything else that might be
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* on this chip select for a VA/PA mapping.
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*/
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/* Internal Memory 1MB */
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AT91RM92_OHCI_BASE,
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AT91RM92_OHCI_PA_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{
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/* CompactFlash controller. Portion of EBI CS4 1MB */
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AT91RM92_CF_BASE,
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AT91RM92_CF_PA_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/* The next two should be good for the 9260, 9261 and 9G20 since
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* addresses mapping is the same. */
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{
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/* Internal Memory 1MB */
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AT91SAM9G20_OHCI_BASE,
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AT91SAM9G20_OHCI_PA_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{
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/* EBI CS3 256MB */
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AT91SAM9G20_NAND_BASE,
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AT91SAM9G20_NAND_PA_BASE,
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AT91SAM9G20_NAND_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{ 0, 0, 0, 0, 0, }
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};
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long
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at91_ramsize(void)
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{
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uint32_t cr, mr;
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int banks, rows, cols, bw;
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if (at91_is_rm92()) {
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uint32_t *SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
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cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
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mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
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banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
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rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
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cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
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bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
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} else {
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/* This should be good for the 9260, 9261, 9G20, 9G35 and 9X25 as addresses
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* and registers are the same */
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uint32_t *SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
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cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
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mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
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banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
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rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
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cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
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bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
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}
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return (1 << (cols + rows + banks + bw));
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}
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void *
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initarm(void *arg, void *arg2)
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{
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struct pv_addr kernel_l1pt;
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struct pv_addr dpcpu;
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int loop, i;
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u_int l1pagetable;
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vm_offset_t freemempos;
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vm_offset_t afterkern;
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uint32_t memsize;
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vm_offset_t lastaddr;
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boot_arg1 = arg;
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boot_arg2 = arg2;
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set_cpufuncs();
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lastaddr = fake_preload_metadata();
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pcpu_init(pcpup, 0, sizeof(struct pcpu));
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PCPU_SET(curthread, &thread0);
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/* Do basic tuning, hz etc */
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init_param1();
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freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
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/* Define a macro to simplify memory allocation */
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#define valloc_pages(var, np) \
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alloc_pages((var).pv_va, (np)); \
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(var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR);
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#define alloc_pages(var, np) \
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(var) = freemempos; \
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freemempos += (np * PAGE_SIZE); \
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memset((char *)(var), 0, ((np) * PAGE_SIZE));
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while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
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freemempos += PAGE_SIZE;
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valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
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for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
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if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
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valloc_pages(kernel_pt_table[loop],
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L2_TABLE_SIZE / PAGE_SIZE);
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} else {
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kernel_pt_table[loop].pv_va = freemempos -
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(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
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L2_TABLE_SIZE_REAL;
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kernel_pt_table[loop].pv_pa =
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kernel_pt_table[loop].pv_va - KERNVIRTADDR +
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KERNPHYSADDR;
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}
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i++;
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}
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/*
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* Allocate a page for the system page mapped to V0x00000000
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* This page will just contain the system vectors and can be
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* shared by all processes.
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*/
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valloc_pages(systempage, 1);
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/* Allocate dynamic per-cpu area. */
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valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
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dpcpu_init((void *)dpcpu.pv_va, 0);
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/* Allocate stacks for all modes */
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valloc_pages(irqstack, IRQ_STACK_SIZE);
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valloc_pages(abtstack, ABT_STACK_SIZE);
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valloc_pages(undstack, UND_STACK_SIZE);
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valloc_pages(kernelstack, KSTACK_PAGES);
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valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
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/*
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* Now we start construction of the L1 page table
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* We start by mapping the L2 page tables into the L1.
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* This means that we can replace L1 mappings later on if necessary
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*/
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l1pagetable = kernel_l1pt.pv_va;
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/* Map the L2 pages tables in the L1 page table */
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pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
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&kernel_pt_table[KERNEL_PT_SYS]);
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for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
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pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
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&kernel_pt_table[KERNEL_PT_KERN + i]);
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pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
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(((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1));
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for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
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pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
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&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
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}
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/* Map the vector page. */
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pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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/* Map the DPCPU pages */
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pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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/* Map the stack pages */
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pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
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IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
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ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
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UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
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KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
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L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
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pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
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msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
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pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
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kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
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}
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pmap_devmap_bootstrap(l1pagetable, at91_devmap);
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cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
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setttb(kernel_l1pt.pv_pa);
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cpu_tlb_flushID();
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cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
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/* Initialize all the clocks, so that the console can work */
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at91_pmc_init_clock();
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/* Get chip id so device drivers know about differences */
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at91_chip_id = *(uint32_t *)(AT91_BASE + AT91_DBGU_BASE + DBGU_C1R);
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cninit();
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memsize = board_init();
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physmem = memsize / PAGE_SIZE;
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/*
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* Pages were allocated during the secondary bootstrap for the
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* stacks for different CPU modes.
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* We must now set the r13 registers in the different CPU modes to
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* point to these stacks.
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* Since the ARM stacks use STMFD etc. we must set r13 to the top end
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* of the stack memory.
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*/
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cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
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set_stackptr(PSR_IRQ32_MODE,
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irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
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set_stackptr(PSR_ABT32_MODE,
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abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
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set_stackptr(PSR_UND32_MODE,
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undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
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/*
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* We must now clean the cache again....
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* Cleaning may be done by reading new data to displace any
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* dirty data in the cache. This will have happened in setttb()
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* but since we are boot strapping the addresses used for the read
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* may have just been remapped and thus the cache could be out
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* of sync. A re-clean after the switch will cure this.
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* After booting there are no gross relocations of the kernel thus
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* this problem will not occur after initarm().
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*/
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cpu_idcache_wbinv_all();
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/* Set stack for exception handlers */
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data_abort_handler_address = (u_int)data_abort_handler;
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prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
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undefined_handler_address = (u_int)undefinedinstruction_bounce;
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undefined_init();
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proc_linkup0(&proc0, &thread0);
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thread0.td_kstack = kernelstack.pv_va;
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thread0.td_pcb = (struct pcb *)
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(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
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thread0.td_pcb->pcb_flags = 0;
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thread0.td_frame = &proc0_tf;
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pcpup->pc_curpcb = thread0.td_pcb;
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arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
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pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1);
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/*
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* ARM_USE_SMALL_ALLOC uses dump_avail, so it must be filled before
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* calling pmap_bootstrap.
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*/
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dump_avail[0] = PHYSADDR;
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dump_avail[1] = PHYSADDR + memsize;
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dump_avail[2] = 0;
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dump_avail[3] = 0;
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pmap_bootstrap(freemempos,
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KERNVIRTADDR + 3 * memsize,
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&kernel_l1pt);
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msgbufp = (void*)msgbufpv.pv_va;
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msgbufinit(msgbufp, msgbufsize);
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mutex_init();
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i = 0;
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#if PHYSADDR != KERNPHYSADDR
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phys_avail[i++] = PHYSADDR;
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phys_avail[i++] = KERNPHYSADDR;
|
|
#endif
|
|
phys_avail[i++] = virtual_avail - KERNVIRTADDR + KERNPHYSADDR;
|
|
phys_avail[i++] = PHYSADDR + memsize;
|
|
phys_avail[i++] = 0;
|
|
phys_avail[i++] = 0;
|
|
init_param2(physmem);
|
|
kdb_init();
|
|
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
|
|
sizeof(struct pcb)));
|
|
}
|