b8b08befd0
bit in PTE. Enable Access Flag in CPU control. With AF enabled each valid mapping needs to have referenced bit in PTE set in order to be able to cache it in the TLB. AP[0] bit is to be used as reference flag. All access permissions are encoded by AP[2:1] wherein AP[1] is in fact "user enable" and AP[2](APX) is "write disable". All mappings are always set to be valid. Reference emulation is performed by setting/clearing reference flag in PTE. md.pvh_attrs are no longer necessary however pv_flags are still being used for now. Marking vm_page as "dirty" or "referenced" is being performed on: - page or flag fault servicing in pmap_fault_fixup(), basing on the fault type - vm_fault servicing in pmap_enter() according to the desired protections and faulty access type Redundant page marking has been removed as on ARM we know exactly when the particular page is referenced or is going to be written. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Sponsored by: The FreeBSD Foundation, Semihalf
711 lines
22 KiB
C
711 lines
22 KiB
C
/*-
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* Copyright (c) 1991 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and William Jolitz of UUNET Technologies Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Derived from hp300 version by Mike Hibler, this version by William
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* Jolitz uses a recursive map [a pde points to the page directory] to
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* map the page tables using the pagetables themselves. This is done to
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* reduce the impact on kernel virtual memory for lots of sparse address
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* space, and to reduce the cost of memory to each process.
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*
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* from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
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* from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
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* from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PMAP_H_
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#define _MACHINE_PMAP_H_
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#include <machine/pte.h>
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#include <machine/cpuconf.h>
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/*
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* Pte related macros
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*/
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#if ARM_ARCH_6 || ARM_ARCH_7A
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#ifdef SMP
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#define PTE_NOCACHE 2
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#else
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#define PTE_NOCACHE 1
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#endif
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#define PTE_CACHE 6
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#define PTE_DEVICE 2
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#define PTE_PAGETABLE 4
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#else
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#define PTE_NOCACHE 1
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#define PTE_CACHE 2
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#define PTE_PAGETABLE 3
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#endif
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enum mem_type {
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STRONG_ORD = 0,
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DEVICE_NOSHARE,
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DEVICE_SHARE,
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NRML_NOCACHE,
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NRML_IWT_OWT,
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NRML_IWB_OWB,
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NRML_IWBA_OWBA
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};
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#ifndef LOCORE
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#include <sys/queue.h>
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#include <sys/_cpuset.h>
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#include <sys/_lock.h>
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#include <sys/_mutex.h>
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#define PDESIZE sizeof(pd_entry_t) /* for assembly files */
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#define PTESIZE sizeof(pt_entry_t) /* for assembly files */
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#ifdef _KERNEL
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#define vtophys(va) pmap_kextract((vm_offset_t)(va))
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#endif
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#define pmap_page_get_memattr(m) ((m)->md.pv_memattr)
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#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
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#define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0)
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void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
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/*
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* Pmap stuff
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*/
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/*
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* This structure is used to hold a virtual<->physical address
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* association and is used mostly by bootstrap code
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*/
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struct pv_addr {
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SLIST_ENTRY(pv_addr) pv_list;
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vm_offset_t pv_va;
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vm_paddr_t pv_pa;
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};
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struct pv_entry;
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struct pv_chunk;
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struct md_page {
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int pvh_attrs;
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vm_memattr_t pv_memattr;
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vm_offset_t pv_kva; /* first kernel VA mapping */
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TAILQ_HEAD(,pv_entry) pv_list;
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};
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struct l1_ttable;
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struct l2_dtable;
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/*
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* The number of L2 descriptor tables which can be tracked by an l2_dtable.
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* A bucket size of 16 provides for 16MB of contiguous virtual address
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* space per l2_dtable. Most processes will, therefore, require only two or
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* three of these to map their whole working set.
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*/
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#define L2_BUCKET_LOG2 4
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#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2)
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/*
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* Given the above "L2-descriptors-per-l2_dtable" constant, the number
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* of l2_dtable structures required to track all possible page descriptors
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* mappable by an L1 translation table is given by the following constants:
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*/
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#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
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#define L2_SIZE (1 << L2_LOG2)
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struct pmap {
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struct mtx pm_mtx;
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u_int8_t pm_domain;
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struct l1_ttable *pm_l1;
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struct l2_dtable *pm_l2[L2_SIZE];
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pd_entry_t *pm_pdir; /* KVA of page directory */
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cpuset_t pm_active; /* active on cpus */
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struct pmap_statistics pm_stats; /* pmap statictics */
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#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
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TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
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#else
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TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
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#endif
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};
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typedef struct pmap *pmap_t;
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#ifdef _KERNEL
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extern struct pmap kernel_pmap_store;
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#define kernel_pmap (&kernel_pmap_store)
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#define pmap_kernel() kernel_pmap
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#define PMAP_ASSERT_LOCKED(pmap) \
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mtx_assert(&(pmap)->pm_mtx, MA_OWNED)
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#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
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#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
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#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
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NULL, MTX_DEF | MTX_DUPOK)
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#define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx)
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#define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
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#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
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#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
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#endif
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/*
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* For each vm_page_t, there is a list of all currently valid virtual
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* mappings of that page. An entry is a pv_entry_t, the list is pv_list.
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*/
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typedef struct pv_entry {
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vm_offset_t pv_va; /* virtual address for mapping */
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TAILQ_ENTRY(pv_entry) pv_list;
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int pv_flags; /* flags (wired, etc...) */
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#if (ARM_MMU_V6 + ARM_MMU_V7) == 0
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pmap_t pv_pmap; /* pmap where mapping lies */
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TAILQ_ENTRY(pv_entry) pv_plist;
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#endif
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} *pv_entry_t;
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/*
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* pv_entries are allocated in chunks per-process. This avoids the
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* need to track per-pmap assignments.
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*/
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#define _NPCM 8
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#define _NPCPV 252
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struct pv_chunk {
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pmap_t pc_pmap;
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TAILQ_ENTRY(pv_chunk) pc_list;
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uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */
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uint32_t pc_dummy[3]; /* aligns pv_chunk to 4KB */
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TAILQ_ENTRY(pv_chunk) pc_lru;
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struct pv_entry pc_pventry[_NPCPV];
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};
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#ifdef _KERNEL
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boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **);
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/*
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* virtual address to page table entry and
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* to physical address. Likewise for alternate address space.
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* Note: these work recursively, thus vtopte of a pte will give
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* the corresponding pde that in turn maps it.
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*/
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/*
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* The current top of kernel VM.
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*/
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extern vm_offset_t pmap_curmaxkvaddr;
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struct pcb;
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void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
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/* Virtual address to page table entry */
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static __inline pt_entry_t *
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vtopte(vm_offset_t va)
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{
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pd_entry_t *pdep;
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pt_entry_t *ptep;
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if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE)
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return (NULL);
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return (ptep);
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}
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extern vm_paddr_t phys_avail[];
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extern vm_offset_t virtual_avail;
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extern vm_offset_t virtual_end;
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void pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt);
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int pmap_change_attr(vm_offset_t, vm_size_t, int);
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void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
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void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa);
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void *pmap_kenter_temp(vm_paddr_t pa, int i);
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void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa);
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vm_paddr_t pmap_kextract(vm_offset_t va);
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void pmap_kremove(vm_offset_t);
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void *pmap_mapdev(vm_offset_t, vm_size_t);
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void pmap_unmapdev(vm_offset_t, vm_size_t);
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vm_page_t pmap_use_pt(pmap_t, vm_offset_t);
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void pmap_debug(int);
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void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int);
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void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *);
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vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int);
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void
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pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
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int cache);
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int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int);
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int pmap_dmap_iscurrent(pmap_t pmap);
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/*
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* Definitions for MMU domains
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*/
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#define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */
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#define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */
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/*
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* The new pmap ensures that page-tables are always mapping Write-Thru.
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* Thus, on some platforms we can run fast and loose and avoid syncing PTEs
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* on every change.
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*
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* Unfortunately, not all CPUs have a write-through cache mode. So we
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* define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
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* and if there is the chance for PTE syncs to be needed, we define
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* PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
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* the code.
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*/
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extern int pmap_needs_pte_sync;
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/*
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* These macros define the various bit masks in the PTE.
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*
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* We use these macros since we use different bits on different processor
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* models.
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*/
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#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
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#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\
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L1_S_XSCALE_TEX(TEX_XSCALE_T))
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#define L2_L_CACHE_MASK_generic (L2_B|L2_C)
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#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \
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L2_XSCALE_L_TEX(TEX_XSCALE_T))
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#define L2_S_PROT_U_generic (L2_AP(AP_U))
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#define L2_S_PROT_W_generic (L2_AP(AP_W))
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#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W)
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#define L2_S_PROT_U_xscale (L2_AP0(AP_U))
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#define L2_S_PROT_W_xscale (L2_AP0(AP_W))
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#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W)
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#define L2_S_CACHE_MASK_generic (L2_B|L2_C)
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#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \
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L2_XSCALE_T_TEX(TEX_XSCALE_X))
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#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP)
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#define L1_S_PROTO_xscale (L1_TYPE_S)
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#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2)
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#define L1_C_PROTO_xscale (L1_TYPE_C)
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#define L2_L_PROTO (L2_TYPE_L)
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#define L2_S_PROTO_generic (L2_TYPE_S)
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#define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS)
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/*
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* User-visible names for the ones that vary with MMU class.
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*/
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#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
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#define L2_AP(x) (L2_AP0(x))
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#else
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#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
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#endif
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#if ARM_NMMUS > 1
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/* More than one MMU class configured; use variables. */
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#define L2_S_PROT_U pte_l2_s_prot_u
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#define L2_S_PROT_W pte_l2_s_prot_w
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#define L2_S_PROT_MASK pte_l2_s_prot_mask
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#define L1_S_CACHE_MASK pte_l1_s_cache_mask
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#define L2_L_CACHE_MASK pte_l2_l_cache_mask
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#define L2_S_CACHE_MASK pte_l2_s_cache_mask
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#define L1_S_PROTO pte_l1_s_proto
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#define L1_C_PROTO pte_l1_c_proto
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#define L2_S_PROTO pte_l2_s_proto
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#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
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#define L2_S_PROT_U L2_S_PROT_U_generic
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#define L2_S_PROT_W L2_S_PROT_W_generic
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#define L2_S_PROT_MASK L2_S_PROT_MASK_generic
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#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic
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#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic
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#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic
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#define L1_S_PROTO L1_S_PROTO_generic
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#define L1_C_PROTO L1_C_PROTO_generic
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#define L2_S_PROTO L2_S_PROTO_generic
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#elif ARM_MMU_XSCALE == 1
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#define L2_S_PROT_U L2_S_PROT_U_xscale
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#define L2_S_PROT_W L2_S_PROT_W_xscale
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#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale
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#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale
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#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale
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#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale
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#define L1_S_PROTO L1_S_PROTO_xscale
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#define L1_C_PROTO L1_C_PROTO_xscale
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#define L2_S_PROTO L2_S_PROTO_xscale
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#elif (ARM_MMU_V6 + ARM_MMU_V7) != 0
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/*
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* AP[2:1] access permissions model:
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*
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* AP[2](APX) - Write Disable
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* AP[1] - User Enable
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* AP[0] - Reference Flag
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*
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* AP[2] AP[1] Kernel User
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* 0 0 R/W N
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* 0 1 R/W R/W
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* 1 0 R N
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* 1 1 R R
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*
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*/
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#define L2_S_PROT_R (0) /* kernel read */
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#define L2_S_PROT_U (L2_AP0(2)) /* user read */
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#define L2_S_REF (L2_AP0(1)) /* reference flag */
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#define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R)
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#define L2_S_WRITABLE(pte) (!(pte & L2_APX))
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#define L2_S_REFERENCED(pte) (!!(pte & L2_S_REF))
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#ifndef SMP
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#define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C)
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#define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C)
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#define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C)
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#else
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#define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED)
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#define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED)
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#define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED)
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#endif /* SMP */
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#define L1_S_PROTO (L1_TYPE_S)
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#define L1_C_PROTO (L1_TYPE_C)
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#define L2_S_PROTO (L2_TYPE_S)
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#ifndef SMP
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#define ARM_L1S_STRONG_ORD (0)
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#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
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#define ARM_L1S_DEVICE_SHARE (L1_S_B)
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#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1))
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#define ARM_L1S_NRML_IWT_OWT (L1_S_C)
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#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B)
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#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B)
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#define ARM_L2L_STRONG_ORD (0)
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#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
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#define ARM_L2L_DEVICE_SHARE (L2_B)
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#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1))
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#define ARM_L2L_NRML_IWT_OWT (L2_C)
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#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B)
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#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B)
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#define ARM_L2S_STRONG_ORD (0)
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#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
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#define ARM_L2S_DEVICE_SHARE (L2_B)
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#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1))
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#define ARM_L2S_NRML_IWT_OWT (L2_C)
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#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B)
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#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B)
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#else
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#define ARM_L1S_STRONG_ORD (0)
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#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
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#define ARM_L1S_DEVICE_SHARE (L1_S_B)
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#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED)
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#define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED)
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#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED)
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#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED)
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#define ARM_L2L_STRONG_ORD (0)
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#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
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#define ARM_L2L_DEVICE_SHARE (L2_B)
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#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED)
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#define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED)
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#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
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#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED)
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#define ARM_L2S_STRONG_ORD (0)
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#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
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#define ARM_L2S_DEVICE_SHARE (L2_B)
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#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED)
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#define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED)
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#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
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#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED)
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#endif /* SMP */
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#endif /* ARM_NMMUS > 1 */
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#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1)
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#define PMAP_NEEDS_PTE_SYNC 1
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#define PMAP_INCLUDE_PTE_SYNC
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#elif defined(CPU_XSCALE_81342)
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#define PMAP_NEEDS_PTE_SYNC 1
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#define PMAP_INCLUDE_PTE_SYNC
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#elif (ARM_MMU_SA1 == 0)
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#define PMAP_NEEDS_PTE_SYNC 0
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#endif
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/*
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* These macros return various bits based on kernel/user and protection.
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* Note that the compiler will usually fold these at compile time.
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*/
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#if (ARM_MMU_V6 + ARM_MMU_V7) == 0
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#define L1_S_PROT_U (L1_S_AP(AP_U))
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#define L1_S_PROT_W (L1_S_AP(AP_W))
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#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W)
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#define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W)
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#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0))
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#define L2_L_PROT_U (L2_AP(AP_U))
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#define L2_L_PROT_W (L2_AP(AP_W))
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#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W)
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#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0))
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|
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#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
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#else
|
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#define L1_S_PROT_U (L1_S_AP(AP_U))
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#define L1_S_PROT_MASK (L1_S_APX|L1_S_AP(0x3))
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#define L1_S_WRITABLE(pd) (!((pd) & L1_S_APX))
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#define L1_S_PROT(ku, pr) (L1_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L1_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L1_S_APX : 0)))
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|
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#define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3))
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#define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
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|
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#define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
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#endif
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/*
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|
* Macros to test if a mapping is mappable with an L1 Section mapping
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* or an L2 Large Page mapping.
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|
*/
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#define L1_S_MAPPABLE_P(va, pa, size) \
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((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
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#define L2_L_MAPPABLE_P(va, pa, size) \
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((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
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|
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/*
|
|
* Provide a fallback in case we were not able to determine it at
|
|
* compile-time.
|
|
*/
|
|
#ifndef PMAP_NEEDS_PTE_SYNC
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#define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync
|
|
#define PMAP_INCLUDE_PTE_SYNC
|
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#endif
|
|
|
|
#define PTE_SYNC(pte) \
|
|
do { \
|
|
if (PMAP_NEEDS_PTE_SYNC) { \
|
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cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
|
|
cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
|
|
} else \
|
|
cpu_drain_writebuf(); \
|
|
} while (/*CONSTCOND*/0)
|
|
|
|
#define PTE_SYNC_RANGE(pte, cnt) \
|
|
do { \
|
|
if (PMAP_NEEDS_PTE_SYNC) { \
|
|
cpu_dcache_wb_range((vm_offset_t)(pte), \
|
|
(cnt) << 2); /* * sizeof(pt_entry_t) */ \
|
|
cpu_l2cache_wb_range((vm_offset_t)(pte), \
|
|
(cnt) << 2); /* * sizeof(pt_entry_t) */ \
|
|
} else \
|
|
cpu_drain_writebuf(); \
|
|
} while (/*CONSTCOND*/0)
|
|
|
|
extern pt_entry_t pte_l1_s_cache_mode;
|
|
extern pt_entry_t pte_l1_s_cache_mask;
|
|
|
|
extern pt_entry_t pte_l2_l_cache_mode;
|
|
extern pt_entry_t pte_l2_l_cache_mask;
|
|
|
|
extern pt_entry_t pte_l2_s_cache_mode;
|
|
extern pt_entry_t pte_l2_s_cache_mask;
|
|
|
|
extern pt_entry_t pte_l1_s_cache_mode_pt;
|
|
extern pt_entry_t pte_l2_l_cache_mode_pt;
|
|
extern pt_entry_t pte_l2_s_cache_mode_pt;
|
|
|
|
extern pt_entry_t pte_l2_s_prot_u;
|
|
extern pt_entry_t pte_l2_s_prot_w;
|
|
extern pt_entry_t pte_l2_s_prot_mask;
|
|
|
|
extern pt_entry_t pte_l1_s_proto;
|
|
extern pt_entry_t pte_l1_c_proto;
|
|
extern pt_entry_t pte_l2_s_proto;
|
|
|
|
extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
|
|
extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
|
|
vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
|
|
extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
|
|
|
|
#if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342)
|
|
void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
|
|
void pmap_zero_page_generic(vm_paddr_t, int, int);
|
|
|
|
void pmap_pte_init_generic(void);
|
|
#if defined(CPU_ARM8)
|
|
void pmap_pte_init_arm8(void);
|
|
#endif
|
|
#if defined(CPU_ARM9)
|
|
void pmap_pte_init_arm9(void);
|
|
#endif /* CPU_ARM9 */
|
|
#if defined(CPU_ARM10)
|
|
void pmap_pte_init_arm10(void);
|
|
#endif /* CPU_ARM10 */
|
|
#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
|
|
void pmap_pte_init_mmu_v6(void);
|
|
#endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */
|
|
#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
|
|
|
|
#if /* ARM_MMU_SA1 == */1
|
|
void pmap_pte_init_sa1(void);
|
|
#endif /* ARM_MMU_SA1 == 1 */
|
|
|
|
#if ARM_MMU_XSCALE == 1
|
|
void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t);
|
|
void pmap_zero_page_xscale(vm_paddr_t, int, int);
|
|
|
|
void pmap_pte_init_xscale(void);
|
|
|
|
void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t);
|
|
|
|
void pmap_use_minicache(vm_offset_t, vm_size_t);
|
|
#endif /* ARM_MMU_XSCALE == 1 */
|
|
#if defined(CPU_XSCALE_81342)
|
|
#define ARM_HAVE_SUPERSECTIONS
|
|
#endif
|
|
|
|
#define PTE_KERNEL 0
|
|
#define PTE_USER 1
|
|
#define l1pte_valid(pde) ((pde) != 0)
|
|
#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
|
|
#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
|
|
#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
|
|
|
|
#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
|
|
#define l2pte_valid(pte) ((pte) != 0)
|
|
#define l2pte_pa(pte) ((pte) & L2_S_FRAME)
|
|
#define l2pte_minidata(pte) (((pte) & \
|
|
(L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\
|
|
== (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))
|
|
|
|
/* L1 and L2 page table macros */
|
|
#define pmap_pde_v(pde) l1pte_valid(*(pde))
|
|
#define pmap_pde_section(pde) l1pte_section_p(*(pde))
|
|
#define pmap_pde_page(pde) l1pte_page_p(*(pde))
|
|
#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde))
|
|
|
|
#define pmap_pte_v(pte) l2pte_valid(*(pte))
|
|
#define pmap_pte_pa(pte) l2pte_pa(*(pte))
|
|
|
|
/*
|
|
* Flags that indicate attributes of pages or mappings of pages.
|
|
*
|
|
* The PVF_MOD and PVF_REF flags are stored in the mdpage for each
|
|
* page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
|
|
* pv_entry's for each page. They live in the same "namespace" so
|
|
* that we can clear multiple attributes at a time.
|
|
*
|
|
* Note the "non-cacheable" flag generally means the page has
|
|
* multiple mappings in a given address space.
|
|
*/
|
|
#define PVF_MOD 0x01 /* page is modified */
|
|
#define PVF_REF 0x02 /* page is referenced */
|
|
#define PVF_WIRED 0x04 /* mapping is wired */
|
|
#define PVF_WRITE 0x08 /* mapping is writable */
|
|
#define PVF_EXEC 0x10 /* mapping is executable */
|
|
#define PVF_NC 0x20 /* mapping is non-cacheable */
|
|
#define PVF_MWC 0x40 /* mapping is used multiple times in userland */
|
|
#define PVF_UNMAN 0x80 /* mapping is unmanaged */
|
|
|
|
void vector_page_setprot(int);
|
|
|
|
/*
|
|
* This structure is used by machine-dependent code to describe
|
|
* static mappings of devices, created at bootstrap time.
|
|
*/
|
|
struct pmap_devmap {
|
|
vm_offset_t pd_va; /* virtual address */
|
|
vm_paddr_t pd_pa; /* physical address */
|
|
vm_size_t pd_size; /* size of region */
|
|
vm_prot_t pd_prot; /* protection code */
|
|
int pd_cache; /* cache attributes */
|
|
};
|
|
|
|
const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t);
|
|
const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t);
|
|
|
|
void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *);
|
|
void pmap_devmap_register(const struct pmap_devmap *);
|
|
|
|
#define SECTION_CACHE 0x1
|
|
#define SECTION_PT 0x2
|
|
void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags);
|
|
#ifdef ARM_HAVE_SUPERSECTIONS
|
|
void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags);
|
|
#endif
|
|
|
|
extern char *_tmppt;
|
|
|
|
void pmap_postinit(void);
|
|
|
|
#ifdef ARM_USE_SMALL_ALLOC
|
|
void arm_add_smallalloc_pages(void *, void *, int, int);
|
|
vm_offset_t arm_ptovirt(vm_paddr_t);
|
|
void arm_init_smallalloc(void);
|
|
struct arm_small_page {
|
|
void *addr;
|
|
TAILQ_ENTRY(arm_small_page) pg_list;
|
|
};
|
|
|
|
#endif
|
|
|
|
#define ARM_NOCACHE_KVA_SIZE 0x1000000
|
|
extern vm_offset_t arm_nocache_startaddr;
|
|
void *arm_remap_nocache(void *, vm_size_t);
|
|
void arm_unmap_nocache(void *, vm_size_t);
|
|
|
|
extern vm_paddr_t dump_avail[];
|
|
#endif /* _KERNEL */
|
|
|
|
#endif /* !LOCORE */
|
|
|
|
#endif /* !_MACHINE_PMAP_H_ */
|