58fb7d8e0b
ahc_pci.c: Prepare for making ahc a module by adding module dependency and version info. aic7770.c: Remove linux header ifdefs. The headers are handled differently in Linux where local includes (those using "'s instead of <>'s) are allowed. Don't map our interrupt until after we are fully setup to handle interrupts. Our interrupt line may be shared so an interrupt could occur at any time. aic7xxx.c: Remove linux header ifdefs. current->curr to avoid Linux's use of current as a #define for the current task on some architectures. Add a helper function, ahc_assert_atn(), for use in message phases we handle manually. This hides the fact that U160 chips with the expected phase matching disabled need to have SCSISIGO updated differently. if (ahc_check_residual(scb) != 0) ahc_calc_residual(scb); else ahc_set_residual(scb, 0); becomes: ahc_update_residual(scb); Modify scsi parity error (or CRC error) handling to reflect expected phase being disabled on U160 chips. Move SELTO handling above BUSFREE handling so we can use the new busfree interrupt behavior on U160 chips. In ahc_build_transfer_msg() filter the period and ppr_options prior to deciding whether a PPR message is required. ppr_options may be forced to zero which will effect our decision. Correct a long standing but latent bug in ahc_find_syncrate(). We could choose a DT only rate even though DT transfers were disabled. In the CAM environment this was unlikely as CAM filters our rate to a non-DT value if the device does not support such rates. When displaing controller characteristics, include the speed of the chip. This way we can modify the transfer speed based on optional features that are enabled/disabled in a particular application. Add support for switching from fully blown tagged queing to just using simple queue tags should the device reject an ordered tag. Remove per-target "current" disconnect and tag queuing enable flags. These should be per-device and are not referenced internally be the driver, so we let the OSM track this state if it needs to. Use SCSI-3 message terminology. aic7xxx.h: The real 7850 does not support Ultra modes, but there are several cards that use the generic 7850 PCI ID even though they are using an Ultra capable chip (7859/7860). We start out with the AHC_ULTRA feature set and then check the DEVSTATUS register to determine if the capability is really present. current -> curr ahc_calc_residual() is no longer static allowing it to be called from ahc_update_residual() in aic7xxx_inline.h. Update some serial eeprom definitions for the latest BIOS versions. aic7xxx.reg: Add a combined DATA_PHASE mask to the SCSIPHASE register definition to simplify some sequencer code. aic7xxx.seq: Take advantage of some performance features available only on the U160 chips. The auto-ack feature allows us to ack data-in phases up to the data-fifo size while the sequencer is still setting up the DMA engine. This greatly reduces read transfer latency and simplifies testing for transfer complete (check SCSIEN only). We also disable the expected phase feature, and enable the new bus free interrupt behavior, to avoid a few instructions. Re-arrange the Ultra2+ data phase handling to allow us to do more work in parallel with the data fifo flushing on a read. On an SDTR, ack the message immediately so the target can prepare the next phase or message byte in parallel with our work to honor the message. aic7xxx_93cx6.c: Remove linux header ifdefs. aic7xxx_freebsd.c: current -> curr Add a module event handler. Handle tag downgrades in our ahc_send_async() handler. We won't be able to downgrade to "basic queuing" until CAM is made aware of this queuing type. aic7xxx_freebsd.h: Include cleanups. Define offsetof if required. Correct a few comments. Update prototype of ahc_send_async(). aic7xxx_inline.h: Implement ahc_update_residual(). aic7xxx_pci.c: Remove linux header ifdefs. Correct a few product strings. Enable several U160 performance enhancing features. Modify Ultra capability determination so we will enable Ultra speeds on devices with a 7850 PCI id that happen to really be a 7859 or 7860. Don't map our interrupt until after we are fully setup to handle interrupts. Our interrupt line may be shared so an interrupt could occur at any time.
206 lines
6.6 KiB
C
206 lines
6.6 KiB
C
/*
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* Interface for the 93C66/56/46/26/06 serial eeprom parts.
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*
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* Copyright (c) 1995, 1996 Daniel M. Eischen
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU Public License ("GPL").
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: //depot/src/aic7xxx/aic7xxx_93cx6.c#7 $
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*
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* $FreeBSD$
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*/
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/*
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* The instruction set of the 93C66/56/46/26/06 chips are as follows:
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*
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* Start OP *
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* Function Bit Code Address** Data Description
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* -------------------------------------------------------------------
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* READ 1 10 A5 - A0 Reads data stored in memory,
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* starting at specified address
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* EWEN 1 00 11XXXX Write enable must precede
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* all programming modes
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* ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0
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* WRITE 1 01 A5 - A0 D15 - D0 Writes register
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* ERAL 1 00 10XXXX Erase all registers
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* WRAL 1 00 01XXXX D15 - D0 Writes to all registers
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* EWDS 1 00 00XXXX Disables all programming
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* instructions
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* *Note: A value of X for address is a don't care condition.
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* **Note: There are 8 address bits for the 93C56/66 chips unlike
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* the 93C46/26/06 chips which have 6 address bits.
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*
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* The 93C46 has a four wire interface: clock, chip select, data in, and
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* data out. In order to perform one of the above functions, you need
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* to enable the chip select for a clock period (typically a minimum of
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* 1 usec, with the clock high and low a minimum of 750 and 250 nsec
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* respectively). While the chip select remains high, you can clock in
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* the instructions (above) starting with the start bit, followed by the
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* OP code, Address, and Data (if needed). For the READ instruction, the
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* requested 16-bit register contents is read from the data out line but
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* is preceded by an initial zero (leading 0, followed by 16-bits, MSB
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* first). The clock cycling from low to high initiates the next data
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* bit to be sent from the chip.
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*
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*/
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#include <dev/aic7xxx/aic7xxx_freebsd.h>
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#include <dev/aic7xxx/aic7xxx_inline.h>
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#include <dev/aic7xxx/aic7xxx_93cx6.h>
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/*
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* Right now, we only have to read the SEEPROM. But we make it easier to
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* add other 93Cx6 functions.
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*/
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static struct seeprom_cmd {
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uint8_t len;
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uint8_t bits[3];
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} seeprom_read = {3, {1, 1, 0}};
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/*
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* Wait for the SEERDY to go high; about 800 ns.
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*/
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#define CLOCK_PULSE(sd, rdy) \
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while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \
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; /* Do nothing */ \
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} \
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(void)SEEPROM_INB(sd); /* Clear clock */
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/*
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* Read the serial EEPROM and returns 1 if successful and 0 if
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* not successful.
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*/
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int
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read_seeprom(sd, buf, start_addr, count)
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struct seeprom_descriptor *sd;
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uint16_t *buf;
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u_int start_addr;
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u_int count;
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{
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int i = 0;
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u_int k = 0;
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uint16_t v;
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uint8_t temp;
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/*
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* Read the requested registers of the seeprom. The loop
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* will range from 0 to count-1.
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*/
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for (k = start_addr; k < count + start_addr; k++) {
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/* Send chip select for one clock cycle. */
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temp = sd->sd_MS ^ sd->sd_CS;
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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/*
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* Now we're ready to send the read command followed by the
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* address of the 16-bit register we want to read.
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*/
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for (i = 0; i < seeprom_read.len; i++) {
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if (seeprom_read.bits[i] != 0)
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temp ^= sd->sd_DO;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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if (seeprom_read.bits[i] != 0)
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temp ^= sd->sd_DO;
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}
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/* Send the 6 or 8 bit address (MSB first, LSB last). */
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for (i = (sd->sd_chip - 1); i >= 0; i--) {
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if ((k & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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if ((k & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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}
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/*
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* Now read the 16 bit register. An initial 0 precedes the
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* register contents which begins with bit 15 (MSB) and ends
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* with bit 0 (LSB). The initial 0 will be shifted off the
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* top of our word as we let the loop run from 0 to 16.
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*/
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v = 0;
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for (i = 16; i >= 0; i--) {
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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v <<= 1;
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if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
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v |= 1;
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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}
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buf[k - start_addr] = v;
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/* Reset the chip select for the next command cycle. */
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temp = sd->sd_MS;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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}
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#ifdef AHC_DUMP_EEPROM
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printf("\nSerial EEPROM:\n\t");
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for (k = 0; k < count; k = k + 1) {
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if (((k % 8) == 0) && (k != 0)) {
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printf ("\n\t");
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}
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printf (" 0x%x", buf[k]);
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}
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printf ("\n");
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#endif
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return (1);
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}
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int
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verify_cksum(struct seeprom_config *sc)
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{
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int i;
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int maxaddr;
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uint32_t checksum;
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uint16_t *scarray;
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maxaddr = (sizeof(*sc)/2) - 1;
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checksum = 0;
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scarray = (uint16_t *)sc;
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for (i = 0; i < maxaddr; i++)
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checksum = checksum + scarray[i];
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if (checksum == 0
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|| (checksum & 0xFFFF) != sc->checksum) {
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return (0);
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} else {
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return(1);
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}
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}
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