492 lines
13 KiB
C
492 lines
13 KiB
C
/*-
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* Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for imx Enhanced Programmable Interval Timer, a simple free-running
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* counter device that can be used as the system timecounter. On imx5 a second
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* instance of the device is used as the system eventtimer.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <machine/machdep.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/freescale/imx/imx_ccmvar.h>
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#include <arm/freescale/imx/imx_machdep.h>
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#define EPIT_CR 0x00 /* Control register */
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#define EPIT_CR_CLKSRC_SHIFT 24
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#define EPIT_CR_CLKSRC_OFF 0
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#define EPIT_CR_CLKSRC_IPG 1
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#define EPIT_CR_CLKSRC_HFCLK 2
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#define EPIT_CR_CLKSRC_LFCLK 3
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#define EPIT_CR_STOPEN (1u << 21)
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#define EPIT_CR_WAITEN (1u << 19)
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#define EPIT_CR_DBGEN (1u << 18)
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#define EPIT_CR_IOVW (1u << 17)
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#define EPIT_CR_SWR (1u << 16)
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#define EPIT_CR_RLD (1u << 3)
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#define EPIT_CR_OCIEN (1u << 2)
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#define EPIT_CR_ENMOD (1u << 1)
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#define EPIT_CR_EN (1u << 0)
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#define EPIT_SR 0x04 /* Status register */
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#define EPIT_SR_OCIF (1u << 0)
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#define EPIT_LR 0x08 /* Load register */
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#define EPIT_CMPR 0x0c /* Compare register */
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#define EPIT_CNR 0x10 /* Counter register */
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/*
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* Define event timer limits.
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*
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* In theory our minimum period is 1 tick, because to setup a oneshot we don't
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* need a read-modify-write sequence to calculate and set a compare register
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* value while the counter is running. In practice the waveform diagrams in the
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* manual make it appear that a setting of 1 might cause it to miss the event,
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* so I'm setting the lower limit to 2 ticks.
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*/
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#define ET_MIN_TICKS 2
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#define ET_MAX_TICKS 0xfffffffe
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static u_int epit_tc_get_timecount(struct timecounter *tc);
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struct epit_softc {
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device_t dev;
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struct resource * memres;
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struct resource * intres;
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void * inthandle;
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uint32_t clkfreq;
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uint32_t ctlreg;
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uint32_t period;
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struct timecounter tc;
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struct eventtimer et;
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bool oneshot;
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};
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/*
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* Probe data. For some reason, the standard linux dts files don't have
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* compatible properties on the epit devices (other properties are missing too,
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* like clocks, but we don't care as much about that). So our probe routine
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* uses the name of the node (must contain "epit") and the address of the
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* registers as identifying marks.
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*/
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static const uint32_t imx51_epit_ioaddr[2] = {0x73fac000, 0x73fb0000};
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static const uint32_t imx53_epit_ioaddr[2] = {0x53fac000, 0x53fb0000};
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static const uint32_t imx6_epit_ioaddr[2] = {0x020d0000, 0x020d4000};
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/* ocd_data is number of units to instantiate on the platform */
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static struct ofw_compat_data compat_data[] = {
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{"fsl,imx6ul-epit", 1},
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{"fsl,imx6sx-epit", 1},
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{"fsl,imx6q-epit", 1},
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{"fsl,imx6dl-epit", 1},
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{"fsl,imx53-epit", 2},
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{"fsl,imx51-epit", 2},
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{"fsl,imx31-epit", 2},
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{"fsl,imx27-epit", 2},
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{"fsl,imx25-epit", 2},
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{NULL, 0}
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};
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static inline uint32_t
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RD4(struct epit_softc *sc, bus_size_t offset)
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{
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return (bus_read_4(sc->memres, offset));
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}
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static inline void
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WR4(struct epit_softc *sc, bus_size_t offset, uint32_t value)
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{
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bus_write_4(sc->memres, offset, value);
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}
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static inline void
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WR4B(struct epit_softc *sc, bus_size_t offset, uint32_t value)
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{
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bus_write_4(sc->memres, offset, value);
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bus_barrier(sc->memres, offset, 4, BUS_SPACE_BARRIER_WRITE);
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}
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static u_int
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epit_read_counter(struct epit_softc *sc)
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{
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/*
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* Hardware is a downcounter, adjust to look like it counts up for use
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* with timecounter and DELAY.
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*/
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return (0xffffffff - RD4(sc, EPIT_CNR));
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}
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static void
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epit_do_delay(int usec, void *arg)
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{
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struct epit_softc *sc = arg;
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uint64_t curcnt, endcnt, startcnt, ticks;
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/*
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* Calculate the tick count with 64-bit values so that it works for any
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* clock frequency. Loop until the hardware count reaches start+ticks.
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* If the 32-bit hardware count rolls over while we're looping, just
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* manually do a carry into the high bits after each read; don't worry
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* that doing this on each loop iteration is inefficient -- we're trying
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* to waste time here.
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*/
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ticks = 1 + ((uint64_t)usec * sc->clkfreq) / 1000000;
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curcnt = startcnt = epit_read_counter(sc);
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endcnt = startcnt + ticks;
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while (curcnt < endcnt) {
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curcnt = epit_read_counter(sc);
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if (curcnt < startcnt)
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curcnt += 1ULL << 32;
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}
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}
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static u_int
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epit_tc_get_timecount(struct timecounter *tc)
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{
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return (epit_read_counter(tc->tc_priv));
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}
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static int
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epit_tc_attach(struct epit_softc *sc)
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{
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/* When the counter hits zero, reload with 0xffffffff. Start it. */
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WR4(sc, EPIT_LR, 0xffffffff);
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WR4(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN);
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/* Register as a timecounter. */
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sc->tc.tc_name = "EPIT";
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sc->tc.tc_quality = 1000;
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sc->tc.tc_frequency = sc->clkfreq;
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sc->tc.tc_counter_mask = 0xffffffff;
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sc->tc.tc_get_timecount = epit_tc_get_timecount;
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sc->tc.tc_priv = sc;
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tc_init(&sc->tc);
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/* We are the DELAY() implementation. */
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arm_set_delay(epit_do_delay, sc);
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return (0);
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}
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static int
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epit_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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{
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struct epit_softc *sc;
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uint32_t ticks;
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sc = (struct epit_softc *)et->et_priv;
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/*
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* Disable the timer and clear any pending status. The timer may be
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* running or may have just expired if we're called to reschedule the
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* next event before the previous event time arrives.
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*/
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WR4(sc, EPIT_CR, sc->ctlreg);
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WR4(sc, EPIT_SR, EPIT_SR_OCIF);
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if (period != 0) {
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sc->oneshot = false;
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ticks = ((uint32_t)et->et_frequency * period) >> 32;
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} else if (first != 0) {
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sc->oneshot = true;
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ticks = ((uint32_t)et->et_frequency * first) >> 32;
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} else {
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return (EINVAL);
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}
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/* Set the countdown load register and start the timer. */
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WR4(sc, EPIT_LR, ticks);
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WR4B(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN);
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return (0);
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}
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static int
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epit_et_stop(struct eventtimer *et)
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{
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struct epit_softc *sc;
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sc = (struct epit_softc *)et->et_priv;
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/* Disable the timer and clear any pending status. */
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WR4(sc, EPIT_CR, sc->ctlreg);
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WR4B(sc, EPIT_SR, EPIT_SR_OCIF);
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return (0);
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}
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static int
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epit_intr(void *arg)
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{
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struct epit_softc *sc;
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uint32_t status;
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sc = arg;
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/*
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* Disable a one-shot timer until a new event is scheduled so that the
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* counter doesn't wrap and fire again. Do this before clearing the
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* status since a short period would make it fire again really soon.
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*
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* Clear interrupt status before invoking event callbacks. The callback
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* often sets up a new one-shot timer event and if the interval is short
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* enough it can fire before we get out of this function. If we cleared
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* at the bottom we'd miss the interrupt and hang until the clock wraps.
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*/
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if (sc->oneshot)
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WR4(sc, EPIT_CR, sc->ctlreg);
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status = RD4(sc, EPIT_SR);
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WR4B(sc, EPIT_SR, status);
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if ((status & EPIT_SR_OCIF) == 0)
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return (FILTER_STRAY);
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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static int
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epit_et_attach(struct epit_softc *sc)
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{
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int err, rid;
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rid = 0;
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sc->intres = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (sc->intres == NULL) {
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device_printf(sc->dev, "could not allocate interrupt\n");
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return (ENXIO);
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}
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err = bus_setup_intr(sc->dev, sc->intres, INTR_TYPE_CLK | INTR_MPSAFE,
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epit_intr, NULL, sc, &sc->inthandle);
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if (err != 0) {
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device_printf(sc->dev, "unable to setup the irq handler\n");
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return (err);
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}
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/* To be an eventtimer, we need interrupts enabled. */
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sc->ctlreg |= EPIT_CR_OCIEN;
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/* Register as an eventtimer. */
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sc->et.et_name = "EPIT";
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sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
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sc->et.et_quality = 1000;
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sc->et.et_frequency = sc->clkfreq;
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sc->et.et_min_period = ((uint64_t)ET_MIN_TICKS << 32) / sc->clkfreq;
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sc->et.et_max_period = ((uint64_t)ET_MAX_TICKS << 32) / sc->clkfreq;
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sc->et.et_start = epit_et_start;
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sc->et.et_stop = epit_et_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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return (0);
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}
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static int
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epit_probe(device_t dev)
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{
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struct resource *memres;
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rman_res_t ioaddr;
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int num_units, rid, unit;
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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/*
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* The FDT data for imx5 and imx6 EPIT hardware is missing or broken,
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* but it may get fixed some day, so first just do a normal check. We
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* return success if the compatible string matches and we haven't
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* already instantiated the number of units needed on this platform.
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*/
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unit = device_get_unit(dev);
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num_units = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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if (unit < num_units) {
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device_set_desc(dev, "i.MX EPIT timer");
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return (BUS_PROBE_DEFAULT);
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}
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/*
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* No compat string match, but for imx6 all the data we need is in the
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* node except the compat string, so do our own compatibility check
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* using the device name of the node and the register block address.
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*/
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if (strstr(ofw_bus_get_name(dev), "epit") == NULL)
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return (ENXIO);
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rid = 0;
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memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_UNMAPPED);
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if (memres == NULL)
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return (ENXIO);
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ioaddr = rman_get_start(memres);
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bus_free_resource(dev, SYS_RES_MEMORY, memres);
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if (imx_soc_family() == 6) {
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if (unit > 0)
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return (ENXIO);
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if (ioaddr != imx6_epit_ioaddr[unit])
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return (ENXIO);
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} else {
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if (unit > 1)
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return (ENXIO);
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switch (imx_soc_type()) {
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case IMXSOC_51:
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if (ioaddr != imx51_epit_ioaddr[unit])
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return (ENXIO);
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break;
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case IMXSOC_53:
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if (ioaddr != imx53_epit_ioaddr[unit])
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return (ENXIO);
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break;
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default:
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return (ENXIO);
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}
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/*
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* XXX Right now we have no way to handle the fact that the
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* entire EPIT node is missing, which means no interrupt data.
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*/
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return (ENXIO);
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}
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device_set_desc(dev, "i.MX EPIT timer");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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epit_attach(device_t dev)
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{
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struct epit_softc *sc;
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int err, rid;
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uint32_t clksrc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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rid = 0;
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sc->memres = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->memres == NULL) {
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device_printf(sc->dev, "could not allocate registers\n");
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return (ENXIO);
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}
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/*
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* For now, use ipg (66 MHz). Some day we should get this from fdt.
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*/
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clksrc = EPIT_CR_CLKSRC_IPG;
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switch (clksrc) {
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default:
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device_printf(dev,
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"Unsupported clock source '%d', using IPG\n", clksrc);
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/* FALLTHROUGH */
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case EPIT_CR_CLKSRC_IPG:
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sc->clkfreq = imx_ccm_ipg_hz();
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break;
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case EPIT_CR_CLKSRC_HFCLK:
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sc->clkfreq = imx_ccm_perclk_hz();
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break;
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case EPIT_CR_CLKSRC_LFCLK:
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sc->clkfreq = 32768;
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break;
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}
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/*
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* Init: stop operations and clear all options, then set up options and
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* clock source, then do a soft-reset and wait for it to complete.
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*/
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WR4(sc, EPIT_CR, 0);
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sc->ctlreg =
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(clksrc << EPIT_CR_CLKSRC_SHIFT) | /* Use selected clock */
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EPIT_CR_ENMOD | /* Reload counter on enable */
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EPIT_CR_RLD | /* Reload counter from LR */
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EPIT_CR_STOPEN | /* Run in STOP mode */
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EPIT_CR_WAITEN | /* Run in WAIT mode */
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EPIT_CR_DBGEN; /* Run in DEBUG mode */
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WR4B(sc, EPIT_CR, sc->ctlreg | EPIT_CR_SWR);
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while (RD4(sc, EPIT_CR) & EPIT_CR_SWR)
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continue;
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/*
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* Unit 0 is the timecounter, 1 (if instantiated) is the eventtimer.
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*/
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if (device_get_unit(sc->dev) == 0)
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err = epit_tc_attach(sc);
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else
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err = epit_et_attach(sc);
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return (err);
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}
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static device_method_t epit_methods[] = {
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DEVMETHOD(device_probe, epit_probe),
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DEVMETHOD(device_attach, epit_attach),
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DEVMETHOD_END
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};
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static driver_t epit_driver = {
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"imx_epit",
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epit_methods,
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sizeof(struct epit_softc),
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};
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static devclass_t epit_devclass;
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EARLY_DRIVER_MODULE(imx_epit, simplebus, epit_driver, epit_devclass, 0,
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0, BUS_PASS_TIMER);
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