333559f2f1
arrays, as elements 0 and 1 of one array and elements 1 and 2 of the other. Run the loop 0..1 instead of 1..2 and use named constants to offset into one of the arrays. PR: 229508
909 lines
22 KiB
C
909 lines
22 KiB
C
/*-
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Oleksandr Rybalko under sponsorship
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* from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Freescale i.MX515 GPIO driver.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <sys/proc.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "gpio_if.h"
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#ifdef INTRNG
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#include "pic_if.h"
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#endif
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#define WRITE4(_sc, _r, _v) \
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bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v))
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#define READ4(_sc, _r) \
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bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r))
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#define SET4(_sc, _r, _m) \
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WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
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#define CLEAR4(_sc, _r, _m) \
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WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
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/* Registers definition for Freescale i.MX515 GPIO controller */
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#define IMX_GPIO_DR_REG 0x000 /* Pin Data */
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#define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */
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#define IMX_GPIO_PSR_REG 0x008 /* Pad Status */
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#define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */
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#define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */
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#define GPIO_ICR_COND_LOW 0
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#define GPIO_ICR_COND_HIGH 1
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#define GPIO_ICR_COND_RISE 2
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#define GPIO_ICR_COND_FALL 3
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#define GPIO_ICR_COND_MASK 0x3
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#define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */
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#define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */
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#define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */
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#ifdef INTRNG
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#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
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GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \
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GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
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#else
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#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
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#endif
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#define NGPIO 32
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#ifdef INTRNG
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struct gpio_irqsrc {
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struct intr_irqsrc gi_isrc;
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u_int gi_irq;
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uint32_t gi_mode;
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};
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#endif
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struct imx51_gpio_softc {
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device_t dev;
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device_t sc_busdev;
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struct mtx sc_mtx;
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struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */
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void *gpio_ih[2];
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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int gpio_npins;
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struct gpio_pin gpio_pins[NGPIO];
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#ifdef INTRNG
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struct gpio_irqsrc gpio_pic_irqsrc[NGPIO];
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#endif
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};
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static struct ofw_compat_data compat_data[] = {
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{"fsl,imx6q-gpio", 1},
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{"fsl,imx53-gpio", 1},
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{"fsl,imx51-gpio", 1},
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{NULL, 0}
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};
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static struct resource_spec imx_gpio_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ -1, 0 }
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};
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#define FIRST_IRQRES 1
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#define NUM_IRQRES 2
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/*
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* Helpers
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*/
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static void imx51_gpio_pin_configure(struct imx51_gpio_softc *,
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struct gpio_pin *, uint32_t);
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/*
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* Driver stuff
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*/
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static int imx51_gpio_probe(device_t);
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static int imx51_gpio_attach(device_t);
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static int imx51_gpio_detach(device_t);
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/*
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* GPIO interface
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*/
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static device_t imx51_gpio_get_bus(device_t);
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static int imx51_gpio_pin_max(device_t, int *);
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static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
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static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
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static int imx51_gpio_pin_getname(device_t, uint32_t, char *);
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static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t);
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static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int);
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static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *);
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static int imx51_gpio_pin_toggle(device_t, uint32_t pin);
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#ifdef INTRNG
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static int
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gpio_pic_map_fdt(struct imx51_gpio_softc *sc, struct intr_map_data_fdt *daf,
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u_int *irqp, uint32_t *modep)
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{
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u_int irq;
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uint32_t mode;
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/*
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* From devicetree/bindings/gpio/fsl-imx-gpio.txt:
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* #interrupt-cells: 2. The first cell is the GPIO number. The second
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* cell bits[3:0] is used to specify trigger type and level flags:
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* 1 = low-to-high edge triggered.
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* 2 = high-to-low edge triggered.
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* 4 = active high level-sensitive.
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* 8 = active low level-sensitive.
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* We can do any single one of these modes, and also edge low+high
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* (i.e., trigger on both edges); other combinations are not supported.
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*/
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if (daf->ncells != 2) {
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device_printf(sc->dev, "Invalid #interrupt-cells\n");
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return (EINVAL);
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}
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irq = daf->cells[0];
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if (irq >= sc->gpio_npins) {
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device_printf(sc->dev, "Invalid interrupt number %u\n", irq);
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return (EINVAL);
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}
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switch (daf->cells[1]) {
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case 1:
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mode = GPIO_INTR_EDGE_RISING;
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break;
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case 2:
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mode = GPIO_INTR_EDGE_FALLING;
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break;
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case 3:
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mode = GPIO_INTR_EDGE_BOTH;
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break;
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case 4:
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mode = GPIO_INTR_LEVEL_HIGH;
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break;
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case 8:
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mode = GPIO_INTR_LEVEL_LOW;
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break;
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default:
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device_printf(sc->dev, "Unsupported interrupt mode 0x%2x\n",
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daf->cells[1]);
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return (ENOTSUP);
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}
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*irqp = irq;
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if (modep != NULL)
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*modep = mode;
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return (0);
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}
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static int
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gpio_pic_map_gpio(struct imx51_gpio_softc *sc, struct intr_map_data_gpio *dag,
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u_int *irqp, uint32_t *modep)
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{
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u_int irq;
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irq = dag->gpio_pin_num;
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if (irq >= sc->gpio_npins) {
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device_printf(sc->dev, "Invalid interrupt number %u\n", irq);
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return (EINVAL);
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}
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switch (dag->gpio_intr_mode) {
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case GPIO_INTR_LEVEL_LOW:
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case GPIO_INTR_LEVEL_HIGH:
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case GPIO_INTR_EDGE_RISING:
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case GPIO_INTR_EDGE_FALLING:
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case GPIO_INTR_EDGE_BOTH:
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break;
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default:
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device_printf(sc->dev, "Unsupported interrupt mode 0x%8x\n",
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dag->gpio_intr_mode);
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return (EINVAL);
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}
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*irqp = irq;
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if (modep != NULL)
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*modep = dag->gpio_intr_mode;
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return (0);
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}
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static int
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gpio_pic_map(struct imx51_gpio_softc *sc, struct intr_map_data *data,
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u_int *irqp, uint32_t *modep)
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{
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switch (data->type) {
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case INTR_MAP_DATA_FDT:
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return (gpio_pic_map_fdt(sc, (struct intr_map_data_fdt *)data,
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irqp, modep));
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case INTR_MAP_DATA_GPIO:
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return (gpio_pic_map_gpio(sc, (struct intr_map_data_gpio *)data,
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irqp, modep));
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default:
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return (ENOTSUP);
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}
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}
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static int
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gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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int error;
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u_int irq;
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struct imx51_gpio_softc *sc;
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sc = device_get_softc(dev);
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error = gpio_pic_map(sc, data, &irq, NULL);
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if (error == 0)
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*isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc;
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return (error);
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}
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static int
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gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct imx51_gpio_softc *sc;
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struct gpio_irqsrc *gi;
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sc = device_get_softc(dev);
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if (isrc->isrc_handlers == 0) {
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gi = (struct gpio_irqsrc *)isrc;
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gi->gi_mode = GPIO_INTR_CONFORM;
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// XXX Not sure this is necessary
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mtx_lock_spin(&sc->sc_mtx);
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CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << gi->gi_irq));
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WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq));
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mtx_unlock_spin(&sc->sc_mtx);
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}
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return (0);
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}
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static int
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gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct imx51_gpio_softc *sc;
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struct gpio_irqsrc *gi;
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int error;
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u_int icfg, irq, reg, shift, wrk;
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uint32_t mode;
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if (data == NULL)
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return (ENOTSUP);
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sc = device_get_softc(dev);
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gi = (struct gpio_irqsrc *)isrc;
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/* Get config for interrupt. */
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error = gpio_pic_map(sc, data, &irq, &mode);
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if (error != 0)
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return (error);
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if (gi->gi_irq != irq)
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return (EINVAL);
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/* Compare config if this is not first setup. */
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if (isrc->isrc_handlers != 0)
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return (gi->gi_mode == mode ? 0 : EINVAL);
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gi->gi_mode = mode;
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/*
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* To interrupt on both edges we have to use the EDGE register. The
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* manual says it only exists for backwards compatibilty with older imx
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* chips, but it's also the only way to configure interrupting on both
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* edges. If the EDGE bit is on, the corresponding ICRn bit is ignored.
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*/
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mtx_lock_spin(&sc->sc_mtx);
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if (mode == GPIO_INTR_EDGE_BOTH) {
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SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq));
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} else {
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CLEAR4(sc, IMX_GPIO_EDGE_REG, (1u << irq));
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switch (mode) {
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default:
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/* silence warnings; default can't actually happen. */
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/* FALLTHROUGH */
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case GPIO_INTR_LEVEL_LOW:
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icfg = GPIO_ICR_COND_LOW;
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break;
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case GPIO_INTR_LEVEL_HIGH:
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icfg = GPIO_ICR_COND_HIGH;
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break;
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case GPIO_INTR_EDGE_RISING:
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icfg = GPIO_ICR_COND_RISE;
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break;
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case GPIO_INTR_EDGE_FALLING:
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icfg = GPIO_ICR_COND_FALL;
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break;
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}
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if (irq < 16) {
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reg = IMX_GPIO_ICR1_REG;
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shift = 2 * irq;
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} else {
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reg = IMX_GPIO_ICR2_REG;
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shift = 2 * (irq - 16);
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}
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wrk = READ4(sc, reg);
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wrk &= ~(GPIO_ICR_COND_MASK << shift);
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wrk |= icfg << shift;
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WRITE4(sc, reg, wrk);
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}
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WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq));
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SET4(sc, IMX_GPIO_IMR_REG, (1u << irq));
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mtx_unlock_spin(&sc->sc_mtx);
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return (0);
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}
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/*
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* this is mask_intr
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*/
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static void
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gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx51_gpio_softc *sc;
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u_int irq;
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sc = device_get_softc(dev);
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irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
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mtx_lock_spin(&sc->sc_mtx);
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CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq));
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mtx_unlock_spin(&sc->sc_mtx);
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}
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/*
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* this is unmask_intr
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*/
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static void
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gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx51_gpio_softc *sc;
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u_int irq;
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sc = device_get_softc(dev);
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irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
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mtx_lock_spin(&sc->sc_mtx);
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SET4(sc, IMX_GPIO_IMR_REG, (1U << irq));
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mtx_unlock_spin(&sc->sc_mtx);
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}
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static void
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gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx51_gpio_softc *sc;
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u_int irq;
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sc = device_get_softc(dev);
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irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
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arm_irq_memory_barrier(0);
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/* EOI. W1C reg so no r-m-w, no locking needed. */
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WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));
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}
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static void
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gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx51_gpio_softc *sc;
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u_int irq;
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sc = device_get_softc(dev);
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irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
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arm_irq_memory_barrier(0);
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/* EOI. W1C reg so no r-m-w, no locking needed. */
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WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));
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gpio_pic_enable_intr(dev, isrc);
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}
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static void
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gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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gpio_pic_disable_intr(dev, isrc);
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}
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static int
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gpio_pic_filter(void *arg)
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{
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struct imx51_gpio_softc *sc;
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struct intr_irqsrc *isrc;
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uint32_t i, interrupts;
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sc = arg;
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mtx_lock_spin(&sc->sc_mtx);
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interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG);
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mtx_unlock_spin(&sc->sc_mtx);
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for (i = 0; interrupts != 0; i++, interrupts >>= 1) {
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if ((interrupts & 0x1) == 0)
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continue;
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isrc = &sc->gpio_pic_irqsrc[i].gi_isrc;
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if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) {
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gpio_pic_disable_intr(sc->dev, isrc);
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gpio_pic_post_filter(sc->dev, isrc);
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device_printf(sc->dev, "Stray irq %u disabled\n", i);
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}
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}
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return (FILTER_HANDLED);
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}
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/*
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* Initialize our isrcs and register them with intrng.
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*/
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static int
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gpio_pic_register_isrcs(struct imx51_gpio_softc *sc)
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{
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int error;
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uint32_t irq;
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const char *name;
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name = device_get_nameunit(sc->dev);
|
|
for (irq = 0; irq < NGPIO; irq++) {
|
|
sc->gpio_pic_irqsrc[irq].gi_irq = irq;
|
|
sc->gpio_pic_irqsrc[irq].gi_mode = GPIO_INTR_CONFORM;
|
|
|
|
error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc,
|
|
sc->dev, 0, "%s,%u", name, irq);
|
|
if (error != 0) {
|
|
/* XXX call intr_isrc_deregister() */
|
|
device_printf(sc->dev, "%s failed", __func__);
|
|
return (error);
|
|
}
|
|
}
|
|
return (0);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin,
|
|
unsigned int flags)
|
|
{
|
|
u_int newflags, pad;
|
|
|
|
mtx_lock_spin(&sc->sc_mtx);
|
|
|
|
/*
|
|
* Manage input/output; other flags not supported yet (maybe not ever,
|
|
* since we have no connection to the pad config registers from here).
|
|
*
|
|
* When setting a pin to output, honor the PRESET_[LOW,HIGH] flags if
|
|
* present. Otherwise, for glitchless transistions on pins with pulls,
|
|
* read the current state of the pad and preset the DR register to drive
|
|
* the current value onto the pin before enabling the pin for output.
|
|
*
|
|
* Note that changes to pin->gp_flags must be acccumulated in newflags
|
|
* and stored with a single writeback to gp_flags at the end, to enable
|
|
* unlocked reads of that value elsewhere. This is only about unlocked
|
|
* access to gp_flags from elsewhere; we still use locking in this
|
|
* function to protect r-m-w access to the hardware registers.
|
|
*/
|
|
if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
|
|
newflags = pin->gp_flags & ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
|
|
if (flags & GPIO_PIN_OUTPUT) {
|
|
if (flags & GPIO_PIN_PRESET_LOW) {
|
|
pad = 0;
|
|
} else if (flags & GPIO_PIN_PRESET_HIGH) {
|
|
pad = 1;
|
|
} else {
|
|
if (flags & GPIO_PIN_OPENDRAIN)
|
|
pad = READ4(sc, IMX_GPIO_PSR_REG);
|
|
else
|
|
pad = READ4(sc, IMX_GPIO_DR_REG);
|
|
pad = (pad >> pin->gp_pin) & 1;
|
|
}
|
|
newflags |= GPIO_PIN_OUTPUT;
|
|
SET4(sc, IMX_GPIO_DR_REG, (pad << pin->gp_pin));
|
|
SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin));
|
|
} else {
|
|
newflags |= GPIO_PIN_INPUT;
|
|
CLEAR4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin));
|
|
}
|
|
pin->gp_flags = newflags;
|
|
}
|
|
|
|
mtx_unlock_spin(&sc->sc_mtx);
|
|
}
|
|
|
|
static device_t
|
|
imx51_gpio_get_bus(device_t dev)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
return (sc->sc_busdev);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_max(device_t dev, int *maxpin)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
*maxpin = sc->gpio_npins - 1;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
*caps = sc->gpio_pins[pin].gp_caps;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
*flags = sc->gpio_pins[pin].gp_flags;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
mtx_lock_spin(&sc->sc_mtx);
|
|
memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME);
|
|
mtx_unlock_spin(&sc->sc_mtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
imx51_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
mtx_lock_spin(&sc->sc_mtx);
|
|
if (value)
|
|
SET4(sc, IMX_GPIO_DR_REG, (1U << pin));
|
|
else
|
|
CLEAR4(sc, IMX_GPIO_DR_REG, (1U << pin));
|
|
mtx_unlock_spin(&sc->sc_mtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
/*
|
|
* Normally a pin set for output can be read by reading the DR reg which
|
|
* indicates what value is being driven to that pin. The exception is
|
|
* pins configured for open-drain mode, in which case we have to read
|
|
* the pad status register in case the pin is being driven externally.
|
|
* Doing so requires that the SION bit be configured in pinmux, which
|
|
* isn't the case for most normal gpio pins, so only try to read via PSR
|
|
* if the OPENDRAIN flag is set, and it's the user's job to correctly
|
|
* configure SION along with open-drain output mode for those pins.
|
|
*/
|
|
if (sc->gpio_pins[pin].gp_flags & GPIO_PIN_OPENDRAIN)
|
|
*val = (READ4(sc, IMX_GPIO_PSR_REG) >> pin) & 1;
|
|
else
|
|
*val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_toggle(device_t dev, uint32_t pin)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
mtx_lock_spin(&sc->sc_mtx);
|
|
WRITE4(sc, IMX_GPIO_DR_REG,
|
|
(READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin)));
|
|
mtx_unlock_spin(&sc->sc_mtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
|
|
uint32_t change_pins, uint32_t *orig_pins)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
if (first_pin != 0)
|
|
return (EINVAL);
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (orig_pins != NULL)
|
|
*orig_pins = READ4(sc, IMX_GPIO_DR_REG);
|
|
|
|
if ((clear_pins | change_pins) != 0) {
|
|
mtx_lock_spin(&sc->sc_mtx);
|
|
WRITE4(sc, IMX_GPIO_DR_REG,
|
|
(READ4(sc, IMX_GPIO_DR_REG) & ~clear_pins) ^ change_pins);
|
|
mtx_unlock_spin(&sc->sc_mtx);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
|
|
uint32_t *pin_flags)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
u_int i;
|
|
uint32_t bit, drclr, drset, flags, oeclr, oeset, pads;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (first_pin != 0 || num_pins > sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
drclr = drset = oeclr = oeset = 0;
|
|
pads = READ4(sc, IMX_GPIO_DR_REG);
|
|
|
|
for (i = 0; i < num_pins; ++i) {
|
|
bit = 1u << i;
|
|
flags = pin_flags[i];
|
|
if (flags & GPIO_PIN_INPUT) {
|
|
oeclr |= bit;
|
|
} else if (flags & GPIO_PIN_OUTPUT) {
|
|
oeset |= bit;
|
|
if (flags & GPIO_PIN_PRESET_LOW)
|
|
drclr |= bit;
|
|
else if (flags & GPIO_PIN_PRESET_HIGH)
|
|
drset |= bit;
|
|
else /* Drive whatever it's now pulled to. */
|
|
drset |= pads & bit;
|
|
}
|
|
}
|
|
|
|
mtx_lock_spin(&sc->sc_mtx);
|
|
WRITE4(sc, IMX_GPIO_DR_REG,
|
|
(READ4(sc, IMX_GPIO_DR_REG) & ~drclr) | drset);
|
|
WRITE4(sc, IMX_GPIO_OE_REG,
|
|
(READ4(sc, IMX_GPIO_OE_REG) & ~oeclr) | oeset);
|
|
mtx_unlock_spin(&sc->sc_mtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
|
|
device_set_desc(dev, "Freescale i.MX GPIO Controller");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_attach(device_t dev)
|
|
{
|
|
struct imx51_gpio_softc *sc;
|
|
int i, irq, unit;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
sc->gpio_npins = NGPIO;
|
|
|
|
mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), NULL, MTX_SPIN);
|
|
|
|
if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) {
|
|
device_printf(dev, "could not allocate resources\n");
|
|
bus_release_resources(dev, imx_gpio_spec, sc->sc_res);
|
|
mtx_destroy(&sc->sc_mtx);
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->sc_iot = rman_get_bustag(sc->sc_res[0]);
|
|
sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]);
|
|
/*
|
|
* Mask off all interrupts in hardware, then set up interrupt handling.
|
|
*/
|
|
WRITE4(sc, IMX_GPIO_IMR_REG, 0);
|
|
for (irq = 0; irq < 2; irq++) {
|
|
#ifdef INTRNG
|
|
if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK,
|
|
gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) {
|
|
device_printf(dev,
|
|
"WARNING: unable to register interrupt handler\n");
|
|
imx51_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
unit = device_get_unit(dev);
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
sc->gpio_pins[i].gp_pin = i;
|
|
sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
|
|
sc->gpio_pins[i].gp_flags =
|
|
(READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT :
|
|
GPIO_PIN_INPUT;
|
|
snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
|
|
"GPIO%d_IO%02d", unit + 1, i);
|
|
}
|
|
|
|
#ifdef INTRNG
|
|
gpio_pic_register_isrcs(sc);
|
|
intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev)));
|
|
#endif
|
|
sc->sc_busdev = gpiobus_attach_bus(dev);
|
|
|
|
if (sc->sc_busdev == NULL) {
|
|
imx51_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx51_gpio_detach(device_t dev)
|
|
{
|
|
int irq;
|
|
struct imx51_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
gpiobus_detach_bus(dev);
|
|
for (irq = 0; irq < NUM_IRQRES; irq++) {
|
|
if (sc->gpio_ih[irq])
|
|
bus_teardown_intr(dev, sc->sc_res[irq + FIRST_IRQRES],
|
|
sc->gpio_ih[irq]);
|
|
}
|
|
bus_release_resources(dev, imx_gpio_spec, sc->sc_res);
|
|
mtx_destroy(&sc->sc_mtx);
|
|
|
|
return(0);
|
|
}
|
|
|
|
static device_method_t imx51_gpio_methods[] = {
|
|
DEVMETHOD(device_probe, imx51_gpio_probe),
|
|
DEVMETHOD(device_attach, imx51_gpio_attach),
|
|
DEVMETHOD(device_detach, imx51_gpio_detach),
|
|
|
|
#ifdef INTRNG
|
|
/* Interrupt controller interface */
|
|
DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr),
|
|
DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr),
|
|
DEVMETHOD(pic_map_intr, gpio_pic_map_intr),
|
|
DEVMETHOD(pic_setup_intr, gpio_pic_setup_intr),
|
|
DEVMETHOD(pic_teardown_intr, gpio_pic_teardown_intr),
|
|
DEVMETHOD(pic_post_filter, gpio_pic_post_filter),
|
|
DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread),
|
|
DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread),
|
|
#endif
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus),
|
|
DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname),
|
|
DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags),
|
|
DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags),
|
|
DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get),
|
|
DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle),
|
|
DEVMETHOD(gpio_pin_access_32, imx51_gpio_pin_access_32),
|
|
DEVMETHOD(gpio_pin_config_32, imx51_gpio_pin_config_32),
|
|
{0, 0},
|
|
};
|
|
|
|
static driver_t imx51_gpio_driver = {
|
|
"gpio",
|
|
imx51_gpio_methods,
|
|
sizeof(struct imx51_gpio_softc),
|
|
};
|
|
static devclass_t imx51_gpio_devclass;
|
|
|
|
EARLY_DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver,
|
|
imx51_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|