ba2c1fbc03
* 286410 * 286413 * 286416 The initial commit broke a variety of debug and features that aren't in the GENERIC kernels but are enabled in other platforms.
771 lines
19 KiB
C
771 lines
19 KiB
C
/*-
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* Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $
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* $FreeBSD$
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*/
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/* USB Requests. */
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#define R92S_REQ_REGS 0x05
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/*
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* MAC registers.
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*/
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#define R92S_SYSCFG 0x0000
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#define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000)
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#define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002)
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#define R92S_PMC_FSM (R92S_SYSCFG + 0x004)
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#define R92S_SYS_CLKR (R92S_SYSCFG + 0x008)
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#define R92S_EE_9346CR (R92S_SYSCFG + 0x00a)
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#define R92S_AFE_MISC (R92S_SYSCFG + 0x010)
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#define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011)
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#define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018)
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#define R92S_RF_CTRL (R92S_SYSCFG + 0x01f)
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#define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020)
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#define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021)
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#define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026)
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#define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028)
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#define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030)
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#define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034)
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#define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8)
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#define R92S_CMDCTRL 0x0040
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#define R92S_CR (R92S_CMDCTRL + 0x000)
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#define R92S_TCR (R92S_CMDCTRL + 0x004)
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#define R92S_RCR (R92S_CMDCTRL + 0x008)
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#define R92S_MACIDSETTING 0x0050
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#define R92S_MACID (R92S_MACIDSETTING + 0x000)
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#define R92S_GP 0x01e0
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#define R92S_GPIO_CTRL (R92S_GP + 0x00c)
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#define R92S_GPIO_IO_SEL (R92S_GP + 0x00e)
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#define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011)
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#define R92S_IOCMD_CTRL 0x0370
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#define R92S_IOCMD_DATA 0x0374
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#define R92S_USB_HRPWM 0xfe58
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/* Bits for R92S_SYS_FUNC_EN. */
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#define R92S_FEN_CPUEN 0x0400
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/* Bits for R92S_PMC_FSM. */
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#define R92S_PMC_FSM_CUT_M 0x000f8000
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#define R92S_PMC_FSM_CUT_S 15
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/* Bits for R92S_SYS_CLKR. */
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#define R92S_SYS_CLKSEL 0x0001
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#define R92S_SYS_PS_CLKSEL 0x0002
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#define R92S_SYS_CPU_CLKSEL 0x0004
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#define R92S_MAC_CLK_EN 0x0800
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#define R92S_SYS_CLK_EN 0x1000
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#define R92S_SWHW_SEL 0x4000
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#define R92S_FWHW_SEL 0x8000
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/* Bits for R92S_EE_9346CR. */
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#define R92S_9356SEL 0x10
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#define R92S_EEPROM_EN 0x20
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/* Bits for R92S_AFE_MISC. */
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#define R92S_AFE_MISC_BGEN 0x01
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#define R92S_AFE_MISC_MBEN 0x02
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#define R92S_AFE_MISC_I32_EN 0x08
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/* Bits for R92S_SPS1_CTRL. */
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#define R92S_SPS1_LDEN 0x01
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#define R92S_SPS1_SWEN 0x02
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/* Bits for R92S_LDOA15_CTRL. */
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#define R92S_LDA15_EN 0x01
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/* Bits for R92S_LDOV12D_CTRL. */
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#define R92S_LDV12_EN 0x01
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/* Bits for R92C_EFUSE_CTRL. */
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#define R92S_EFUSE_CTRL_DATA_M 0x000000ff
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#define R92S_EFUSE_CTRL_DATA_S 0
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#define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00
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#define R92S_EFUSE_CTRL_ADDR_S 8
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#define R92S_EFUSE_CTRL_VALID 0x80000000
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/* Bits for R92S_CR. */
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#define R92S_CR_TXDMA_EN 0x10
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/* Bits for R92S_TCR. */
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#define R92S_TCR_IMEM_CODE_DONE 0x01
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#define R92S_TCR_IMEM_CHK_RPT 0x02
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#define R92S_TCR_EMEM_CODE_DONE 0x04
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#define R92S_TCR_EMEM_CHK_RPT 0x08
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#define R92S_TCR_DMEM_CODE_DONE 0x10
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#define R92S_TCR_IMEM_RDY 0x20
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#define R92S_TCR_FWRDY 0x80
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/* Bits for R92S_GPIO_IO_SEL. */
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#define R92S_GPIO_WPS 0x10
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/* Bits for R92S_MAC_PINMUX_CTRL. */
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#define R92S_GPIOSEL_GPIO_M 0x03
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#define R92S_GPIOSEL_GPIO_S 0
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#define R92S_GPIOSEL_GPIO_JTAG 0
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#define R92S_GPIOSEL_GPIO_PHYDBG 1
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#define R92S_GPIOSEL_GPIO_BT 2
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#define R92S_GPIOSEL_GPIO_WLANDBG 3
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#define R92S_GPIOMUX_EN 0x08
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/* Bits for R92S_IOCMD_CTRL. */
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#define R92S_IOCMD_CLASS_M 0xff000000
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#define R92S_IOCMD_CLASS_S 24
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#define R92S_IOCMD_CLASS_BB_RF 0xf0
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#define R92S_IOCMD_VALUE_M 0x00ffff00
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#define R92S_IOCMD_VALUE_S 8
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#define R92S_IOCMD_INDEX_M 0x000000ff
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#define R92S_IOCMD_INDEX_S 0
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#define R92S_IOCMD_INDEX_BB_READ 0
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#define R92S_IOCMD_INDEX_BB_WRITE 1
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#define R92S_IOCMD_INDEX_RF_READ 2
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#define R92S_IOCMD_INDEX_RF_WRITE 3
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/* Bits for R92S_USB_HRPWM. */
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#define R92S_USB_HRPWM_PS_ALL_ON 0x04
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#define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08
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/*
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* Macros to access subfields in registers.
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*/
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/* Mask and Shift (getter). */
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#define MS(val, field) \
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(((val) & field##_M) >> field##_S)
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/* Shift and Mask (setter). */
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#define SM(field, val) \
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(((val) << field##_S) & field##_M)
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/* Rewrite. */
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#define RW(var, field, val) \
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(((var) & ~field##_M) | SM(field, val))
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/*
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* Firmware image header.
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*/
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struct r92s_fw_priv {
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/* QWORD0 */
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uint16_t signature;
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uint8_t hci_sel;
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#define R92S_HCI_SEL_PCIE 0x01
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#define R92S_HCI_SEL_USB 0x02
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#define R92S_HCI_SEL_SDIO 0x04
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#define R92S_HCI_SEL_8172 0x10
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#define R92S_HCI_SEL_AP 0x80
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uint8_t chip_version;
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uint16_t custid;
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uint8_t rf_config;
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uint8_t nendpoints;
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/* QWORD1 */
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uint32_t regulatory;
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uint8_t rfintfs;
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uint8_t def_nettype;
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uint8_t turbo_mode;
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uint8_t lowpower_mode;
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/* QWORD2 */
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uint8_t lbk_mode;
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uint8_t mp_mode;
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uint8_t vcs_type;
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#define R92S_VCS_TYPE_DISABLE 0
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#define R92S_VCS_TYPE_ENABLE 1
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#define R92S_VCS_TYPE_AUTO 2
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uint8_t vcs_mode;
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#define R92S_VCS_MODE_NONE 0
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#define R92S_VCS_MODE_RTS_CTS 1
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#define R92S_VCS_MODE_CTS2SELF 2
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uint32_t reserved1;
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/* QWORD3 */
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uint8_t qos_en;
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uint8_t bw40_en;
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uint8_t amsdu2ampdu_en;
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uint8_t ampdu_en;
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uint8_t rc_offload;
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uint8_t agg_offload;
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uint16_t reserved2;
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/* QWORD4 */
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uint8_t beacon_offload;
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uint8_t mlme_offload;
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uint8_t hwpc_offload;
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uint8_t tcpcsum_offload;
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uint8_t tcp_offload;
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uint8_t ps_offload;
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uint8_t wwlan_offload;
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uint8_t reserved3;
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/* QWORD5 */
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uint16_t tcp_tx_len;
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uint16_t tcp_rx_len;
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uint32_t reserved4;
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} __packed;
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struct r92s_fw_hdr {
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uint16_t signature;
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uint16_t version;
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uint32_t dmemsz;
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uint32_t imemsz;
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uint32_t sramsz;
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uint32_t privsz;
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uint16_t efuse_addr;
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uint16_t h2c_resp_addr;
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uint32_t svnrev;
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uint8_t month;
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uint8_t day;
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uint8_t hour;
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uint8_t minute;
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struct r92s_fw_priv priv;
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} __packed;
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/* Structure for FW commands and FW events notifications. */
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struct r92s_fw_cmd_hdr {
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uint16_t len;
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uint8_t code;
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uint8_t seq;
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#define R92S_FW_CMD_MORE 0x80
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uint32_t reserved;
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} __packed;
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/* FW commands codes. */
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#define R92S_CMD_READ_MACREG 0
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#define R92S_CMD_WRITE_MACREG 1
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#define R92S_CMD_READ_BBREG 2
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#define R92S_CMD_WRITE_BBREG 3
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#define R92S_CMD_READ_RFREG 4
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#define R92S_CMD_WRITE_RFREG 5
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#define R92S_CMD_READ_EEPROM 6
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#define R92S_CMD_WRITE_EEPROM 7
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#define R92S_CMD_READ_EFUSE 8
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#define R92S_CMD_WRITE_EFUSE 9
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#define R92S_CMD_READ_CAM 10
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#define R92S_CMD_WRITE_CAM 11
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#define R92S_CMD_SET_BCNITV 12
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#define R92S_CMD_SET_MBIDCFG 13
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#define R92S_CMD_JOIN_BSS 14
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#define R92S_CMD_DISCONNECT 15
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#define R92S_CMD_CREATE_BSS 16
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#define R92S_CMD_SET_OPMODE 17
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#define R92S_CMD_SITE_SURVEY 18
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#define R92S_CMD_SET_AUTH 19
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#define R92S_CMD_SET_KEY 20
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#define R92S_CMD_SET_STA_KEY 21
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#define R92S_CMD_SET_ASSOC_STA 22
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#define R92S_CMD_DEL_ASSOC_STA 23
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#define R92S_CMD_SET_STAPWRSTATE 24
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#define R92S_CMD_SET_BASIC_RATE 25
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#define R92S_CMD_GET_BASIC_RATE 26
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#define R92S_CMD_SET_DATA_RATE 27
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#define R92S_CMD_GET_DATA_RATE 28
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#define R92S_CMD_SET_PHY_INFO 29
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#define R92S_CMD_GET_PHY_INFO 30
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#define R92S_CMD_SET_PHY 31
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#define R92S_CMD_GET_PHY 32
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#define R92S_CMD_READ_RSSI 33
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#define R92S_CMD_READ_GAIN 34
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#define R92S_CMD_SET_ATIM 35
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#define R92S_CMD_SET_PWR_MODE 36
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#define R92S_CMD_JOIN_BSS_RPT 37
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#define R92S_CMD_SET_RA_TABLE 38
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#define R92S_CMD_GET_RA_TABLE 39
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#define R92S_CMD_GET_CCX_REPORT 40
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#define R92S_CMD_GET_DTM_REPORT 41
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#define R92S_CMD_GET_TXRATE_STATS 42
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#define R92S_CMD_SET_USB_SUSPEND 43
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#define R92S_CMD_SET_H2C_LBK 44
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#define R92S_CMD_ADDBA_REQ 45
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#define R92S_CMD_SET_CHANNEL 46
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#define R92S_CMD_SET_TXPOWER 47
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#define R92S_CMD_SWITCH_ANTENNA 48
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#define R92S_CMD_SET_CRYSTAL_CAL 49
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#define R92S_CMD_SET_SINGLE_CARRIER_TX 50
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#define R92S_CMD_SET_SINGLE_TONE_TX 51
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#define R92S_CMD_SET_CARRIER_SUPPR_TX 52
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#define R92S_CMD_SET_CONTINUOUS_TX 53
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#define R92S_CMD_SWITCH_BANDWIDTH 54
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#define R92S_CMD_TX_BEACON 55
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#define R92S_CMD_SET_POWER_TRACKING 56
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#define R92S_CMD_AMSDU_TO_AMPDU 57
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#define R92S_CMD_SET_MAC_ADDRESS 58
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#define R92S_CMD_GET_H2C_LBK 59
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#define R92S_CMD_SET_PBREQ_IE 60
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#define R92S_CMD_SET_ASSOCREQ_IE 61
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#define R92S_CMD_SET_PBRESP_IE 62
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#define R92S_CMD_SET_ASSOCRESP_IE 63
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#define R92S_CMD_GET_CURDATARATE 64
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#define R92S_CMD_GET_TXRETRY_CNT 65
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#define R92S_CMD_GET_RXRETRY_CNT 66
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#define R92S_CMD_GET_BCNOK_CNT 67
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#define R92S_CMD_GET_BCNERR_CNT 68
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#define R92S_CMD_GET_CURTXPWR_LEVEL 69
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#define R92S_CMD_SET_DIG 70
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#define R92S_CMD_SET_RA 71
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#define R92S_CMD_SET_PT 72
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#define R92S_CMD_READ_TSSI 73
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/* FW events notifications codes. */
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#define R92S_EVT_READ_MACREG 0
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#define R92S_EVT_READ_BBREG 1
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#define R92S_EVT_READ_RFREG 2
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#define R92S_EVT_READ_EEPROM 3
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#define R92S_EVT_READ_EFUSE 4
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#define R92S_EVT_READ_CAM 5
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#define R92S_EVT_GET_BASICRATE 6
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#define R92S_EVT_GET_DATARATE 7
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#define R92S_EVT_SURVEY 8
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#define R92S_EVT_SURVEY_DONE 9
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#define R92S_EVT_JOIN_BSS 10
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#define R92S_EVT_ADD_STA 11
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#define R92S_EVT_DEL_STA 12
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#define R92S_EVT_ATIM_DONE 13
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#define R92S_EVT_TX_REPORT 14
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#define R92S_EVT_CCX_REPORT 15
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#define R92S_EVT_DTM_REPORT 16
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#define R92S_EVT_TXRATE_STATS 17
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#define R92S_EVT_C2H_LBK 18
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#define R92S_EVT_FWDBG 19
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#define R92S_EVT_C2H_FEEDBACK 20
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#define R92S_EVT_ADDBA 21
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#define R92S_EVT_C2H_BCN 22
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#define R92S_EVT_PWR_STATE 23
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#define R92S_EVT_WPS_PBC 24
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#define R92S_EVT_ADDBA_REQ_REPORT 25
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/* Structure for R92S_CMD_SITE_SURVEY. */
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struct r92s_fw_cmd_sitesurvey {
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uint32_t active;
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uint32_t limit;
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uint32_t ssidlen;
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uint8_t ssid[32 + 1];
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} __packed;
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/* Structure for R92S_CMD_SET_AUTH. */
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struct r92s_fw_cmd_auth {
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uint8_t mode;
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#define R92S_AUTHMODE_OPEN 0
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#define R92S_AUTHMODE_SHARED 1
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#define R92S_AUTHMODE_WPA 2
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uint8_t dot1x;
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} __packed;
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/* Structure for R92S_CMD_SET_KEY. */
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struct r92s_fw_cmd_set_key {
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uint8_t algo;
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#define R92S_KEY_ALGO_NONE 0
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#define R92S_KEY_ALGO_WEP40 1
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#define R92S_KEY_ALGO_TKIP 2
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#define R92S_KEY_ALGO_TKIP_MMIC 3
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#define R92S_KEY_ALGO_AES 4
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#define R92S_KEY_ALGO_WEP104 5
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uint8_t id;
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uint8_t grpkey;
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uint8_t key[16];
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} __packed;
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/* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */
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/* NDIS_802_11_SSID. */
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struct ndis_802_11_ssid {
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uint32_t ssidlen;
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uint8_t ssid[32];
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} __packed;
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/* NDIS_802_11_CONFIGURATION_FH. */
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struct ndis_802_11_configuration_fh {
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uint32_t len;
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uint32_t hoppattern;
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uint32_t hopset;
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uint32_t dwelltime;
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} __packed;
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/* NDIS_802_11_CONFIGURATION. */
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struct ndis_802_11_configuration {
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uint32_t len;
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uint32_t bintval;
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uint32_t atim;
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uint32_t dsconfig;
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struct ndis_802_11_configuration_fh fhconfig;
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} __packed;
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/* NDIS_WLAN_BSSID_EX. */
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struct ndis_wlan_bssid_ex {
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uint32_t len;
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uint8_t macaddr[IEEE80211_ADDR_LEN];
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uint8_t reserved[2];
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struct ndis_802_11_ssid ssid;
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uint32_t privacy;
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int32_t rssi;
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uint32_t networktype;
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#define NDIS802_11FH 0
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#define NDIS802_11DS 1
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#define NDIS802_11OFDM5 2
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#define NDIS802_11OFDM24 3
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#define NDIS802_11AUTOMODE 4
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struct ndis_802_11_configuration config;
|
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uint32_t inframode;
|
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#define NDIS802_11IBSS 0
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#define NDIS802_11INFRASTRUCTURE 1
|
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#define NDIS802_11AUTOUNKNOWN 2
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#define NDIS802_11MONITOR 3
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#define NDIS802_11APMODE 4
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uint8_t supprates[16];
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uint32_t ieslen;
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/* Followed by ``ieslen'' bytes. */
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|
} __packed;
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|
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/* NDIS_802_11_FIXED_IEs. */
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struct ndis_802_11_fixed_ies {
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uint8_t tstamp[8];
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uint16_t bintval;
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uint16_t capabilities;
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} __packed;
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/* Structure for R92S_CMD_SET_PWR_MODE. */
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struct r92s_set_pwr_mode {
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uint8_t mode;
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#define R92S_PS_MODE_ACTIVE 0
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#define R92S_PS_MODE_MIN 1
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#define R92S_PS_MODE_MAX 2
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#define R92S_PS_MODE_DTIM 3
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#define R92S_PS_MODE_VOIP 4
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#define R92S_PS_MODE_UAPSD_WMM 5
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#define R92S_PS_MODE_UAPSD 6
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#define R92S_PS_MODE_IBSS 7
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#define R92S_PS_MODE_WWLAN 8
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#define R92S_PS_MODE_RADIOOFF 9
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#define R92S_PS_MODE_DISABLE 10
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uint8_t low_traffic_en;
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uint8_t lpnav_en;
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uint8_t rf_low_snr_en;
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uint8_t dps_en;
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uint8_t bcn_rx_en;
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uint8_t bcn_pass_cnt;
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uint8_t bcn_to;
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uint16_t bcn_itv;
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uint8_t app_itv;
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uint8_t awake_bcn_itv;
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uint8_t smart_ps;
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uint8_t bcn_pass_time;
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} __packed;
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/* Structure for event R92S_EVENT_JOIN_BSS. */
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struct r92s_event_join_bss {
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uint32_t next;
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uint32_t prev;
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uint32_t networktype;
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uint32_t fixed;
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uint32_t lastscanned;
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uint32_t associd;
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uint32_t join_res;
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struct ndis_wlan_bssid_ex bss;
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} __packed;
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#define R92S_MACID_BSS 5
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/* Rx MAC descriptor. */
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struct r92s_rx_stat {
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uint32_t rxdw0;
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#define R92S_RXDW0_PKTLEN_M 0x00003fff
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#define R92S_RXDW0_PKTLEN_S 0
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#define R92S_RXDW0_CRCERR 0x00004000
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#define R92S_RXDW0_INFOSZ_M 0x000f0000
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#define R92S_RXDW0_INFOSZ_S 16
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#define R92S_RXDW0_QOS 0x00800000
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#define R92S_RXDW0_SHIFT_M 0x03000000
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#define R92S_RXDW0_SHIFT_S 24
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#define R92S_RXDW0_DECRYPTED 0x08000000
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uint32_t rxdw1;
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#define R92S_RXDW1_MOREFRAG 0x08000000
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uint32_t rxdw2;
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#define R92S_RXDW2_FRAG_M 0x0000f000
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#define R92S_RXDW2_FRAG_S 12
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#define R92S_RXDW2_PKTCNT_M 0x00ff0000
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#define R92S_RXDW2_PKTCNT_S 16
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uint32_t rxdw3;
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#define R92S_RXDW3_RATE_M 0x0000003f
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#define R92S_RXDW3_RATE_S 0
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#define R92S_RXDW3_TCPCHKRPT 0x00000800
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#define R92S_RXDW3_IPCHKRPT 0x00001000
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#define R92S_RXDW3_TCPCHKVALID 0x00002000
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#define R92S_RXDW3_HTC 0x00004000
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uint32_t rxdw4;
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uint32_t rxdw5;
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} __packed __aligned(4);
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/* Rx PHY descriptor. */
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struct r92s_rx_phystat {
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uint32_t phydw0;
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uint32_t phydw1;
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uint32_t phydw2;
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uint32_t phydw3;
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uint32_t phydw4;
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uint32_t phydw5;
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uint32_t phydw6;
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uint32_t phydw7;
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} __packed __aligned(4);
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/* Rx PHY CCK descriptor. */
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struct r92s_rx_cck {
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uint8_t adc_pwdb[4];
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uint8_t sq_rpt;
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uint8_t agc_rpt;
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} __packed;
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/* Tx MAC descriptor. */
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struct r92s_tx_desc {
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uint32_t txdw0;
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#define R92S_TXDW0_PKTLEN_M 0x0000ffff
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#define R92S_TXDW0_PKTLEN_S 0
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#define R92S_TXDW0_OFFSET_M 0x00ff0000
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#define R92S_TXDW0_OFFSET_S 16
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#define R92S_TXDW0_TYPE_M 0x03000000
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#define R92S_TXDW0_TYPE_S 24
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#define R92S_TXDW0_LSG 0x04000000
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#define R92S_TXDW0_FSG 0x08000000
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#define R92S_TXDW0_LINIP 0x10000000
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#define R92S_TXDW0_OWN 0x80000000
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|
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uint32_t txdw1;
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#define R92S_TXDW1_MACID_M 0x0000001f
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#define R92S_TXDW1_MACID_S 0
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#define R92S_TXDW1_MOREDATA 0x00000020
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#define R92S_TXDW1_MOREFRAG 0x00000040
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#define R92S_TXDW1_QSEL_M 0x00001f00
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#define R92S_TXDW1_QSEL_S 8
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#define R92S_TXDW1_QSEL_BE 0x03
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#define R92S_TXDW1_QSEL_H2C 0x1f
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#define R92S_TXDW1_NONQOS 0x00010000
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#define R92S_TXDW1_KEYIDX_M 0x00060000
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#define R92S_TXDW1_KEYIDX_S 17
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#define R92S_TXDW1_CIPHER_M 0x00c00000
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#define R92S_TXDW1_CIPHER_S 22
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#define R92S_TXDW1_CIPHER_WEP 1
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#define R92S_TXDW1_CIPHER_TKIP 2
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#define R92S_TXDW1_CIPHER_AES 3
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#define R92S_TXDW1_HWPC 0x80000000
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uint32_t txdw2;
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#define R92S_TXDW2_BMCAST 0x00000080
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#define R92S_TXDW2_AGGEN 0x20000000
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#define R92S_TXDW2_BK 0x40000000
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uint32_t txdw3;
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#define R92S_TXDW3_SEQ_M 0x0fff0000
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#define R92S_TXDW3_SEQ_S 16
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#define R92S_TXDW3_FRAG_M 0xf0000000
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#define R92S_TXDW3_FRAG_S 28
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uint32_t txdw4;
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#define R92S_TXDW4_TXBW 0x00040000
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uint32_t txdw5;
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#define R92S_TXDW5_DISFB 0x00008000
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uint16_t ipchksum;
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uint16_t tcpchksum;
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uint16_t txbufsize;
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|
uint16_t reserved1;
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} __packed __aligned(4);
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|
|
|
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/*
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* Driver definitions.
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|
*/
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#define RSU_RX_LIST_COUNT 1
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#define RSU_TX_LIST_COUNT 32
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|
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#define RSU_HOST_CMD_RING_COUNT 32
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|
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#define RSU_RXBUFSZ (8 * 1024)
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#define RSU_TXBUFSZ \
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((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3)
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#define RSU_TX_TIMEOUT 5000 /* ms */
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#define RSU_CMD_TIMEOUT 2000 /* ms */
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/* Queue ids (used by soft only). */
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#define RSU_QID_BCN 0
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#define RSU_QID_MGT 1
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#define RSU_QID_BMC 2
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#define RSU_QID_VO 3
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|
#define RSU_QID_VI 4
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#define RSU_QID_BE 5
|
|
#define RSU_QID_BK 6
|
|
#define RSU_QID_RXOFF 7
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#define RSU_QID_H2C 8
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#define RSU_QID_C2H 9
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|
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/* Map AC to queue id. */
|
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static const uint8_t rsu_ac2qid[WME_NUM_AC] = {
|
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RSU_QID_BE,
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RSU_QID_BK,
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RSU_QID_VI,
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RSU_QID_VO
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};
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|
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/* Pipe index to endpoint address mapping. */
|
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static const uint8_t r92s_epaddr[] =
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{ 0x83, 0x04, 0x06, 0x0d,
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0x05, 0x07,
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0x89, 0x0a, 0x0b, 0x0c };
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|
|
/* Queue id to pipe index mapping for 4 endpoints configurations. */
|
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static const uint8_t rsu_qid2idx_4ep[] =
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{ 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 };
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|
|
/* Queue id to pipe index mapping for 6 endpoints configurations. */
|
|
static const uint8_t rsu_qid2idx_6ep[] =
|
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{ 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 };
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|
|
/* Queue id to pipe index mapping for 11 endpoints configurations. */
|
|
static const uint8_t rsu_qid2idx_11ep[] =
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{ 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 };
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|
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struct rsu_rx_radiotap_header {
|
|
struct ieee80211_radiotap_header wr_ihdr;
|
|
uint8_t wr_flags;
|
|
uint8_t wr_rate;
|
|
uint16_t wr_chan_freq;
|
|
uint16_t wr_chan_flags;
|
|
uint8_t wr_dbm_antsignal;
|
|
} __packed __aligned(8);
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|
|
|
#define RSU_RX_RADIOTAP_PRESENT \
|
|
(1 << IEEE80211_RADIOTAP_FLAGS | \
|
|
1 << IEEE80211_RADIOTAP_RATE | \
|
|
1 << IEEE80211_RADIOTAP_CHANNEL | \
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|
1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)
|
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|
|
struct rsu_tx_radiotap_header {
|
|
struct ieee80211_radiotap_header wt_ihdr;
|
|
uint8_t wt_flags;
|
|
uint16_t wt_chan_freq;
|
|
uint16_t wt_chan_flags;
|
|
} __packed __aligned(8);
|
|
|
|
#define RSU_TX_RADIOTAP_PRESENT \
|
|
(1 << IEEE80211_RADIOTAP_FLAGS | \
|
|
1 << IEEE80211_RADIOTAP_CHANNEL)
|
|
|
|
struct rsu_softc;
|
|
|
|
struct rsu_host_cmd {
|
|
void (*cb)(struct rsu_softc *, void *);
|
|
uint8_t data[256];
|
|
};
|
|
|
|
struct rsu_cmd_newstate {
|
|
enum ieee80211_state state;
|
|
int arg;
|
|
};
|
|
|
|
struct rsu_cmd_key {
|
|
struct ieee80211_key key;
|
|
};
|
|
|
|
struct rsu_host_cmd_ring {
|
|
struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT];
|
|
int cur;
|
|
int next;
|
|
int queued;
|
|
};
|
|
|
|
enum {
|
|
RSU_BULK_RX,
|
|
RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */
|
|
RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */
|
|
RSU_N_TRANSFER,
|
|
};
|
|
|
|
struct rsu_data {
|
|
struct rsu_softc *sc;
|
|
uint8_t *buf;
|
|
uint16_t buflen;
|
|
struct mbuf *m;
|
|
struct ieee80211_node *ni;
|
|
STAILQ_ENTRY(rsu_data) next;
|
|
};
|
|
|
|
struct rsu_vap {
|
|
struct ieee80211vap vap;
|
|
struct ieee80211_beacon_offsets bo;
|
|
|
|
int (*newstate)(struct ieee80211vap *,
|
|
enum ieee80211_state, int);
|
|
};
|
|
#define RSU_VAP(vap) ((struct rsu_vap *)(vap))
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|
|
#define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
|
|
#define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
|
|
#define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
|
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|
|
struct rsu_softc {
|
|
struct ifnet *sc_ifp;
|
|
device_t sc_dev;
|
|
struct usb_device *sc_udev;
|
|
int (*sc_newstate)(struct ieee80211com *,
|
|
enum ieee80211_state, int);
|
|
struct usbd_interface *sc_iface;
|
|
struct timeout_task calib_task;
|
|
const uint8_t *qid2idx;
|
|
struct mtx sc_mtx;
|
|
|
|
u_int cut;
|
|
int scan_pass;
|
|
struct rsu_host_cmd_ring cmdq;
|
|
struct rsu_data sc_rx[RSU_RX_LIST_COUNT];
|
|
struct rsu_data sc_tx[RSU_TX_LIST_COUNT];
|
|
struct rsu_data *fwcmd_data;
|
|
uint8_t cmd_seq;
|
|
uint8_t rom[128];
|
|
uint8_t sc_bssid[IEEE80211_ADDR_LEN];
|
|
struct usb_xfer *sc_xfer[RSU_N_TRANSFER];
|
|
uint8_t sc_calibrating;
|
|
|
|
STAILQ_HEAD(, rsu_data) sc_rx_active;
|
|
STAILQ_HEAD(, rsu_data) sc_rx_inactive;
|
|
STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER];
|
|
STAILQ_HEAD(, rsu_data) sc_tx_inactive;
|
|
STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER];
|
|
|
|
union {
|
|
struct rsu_rx_radiotap_header th;
|
|
uint8_t pad[64];
|
|
} sc_rxtapu;
|
|
#define sc_rxtap sc_rxtapu.th
|
|
int sc_rxtap_len;
|
|
|
|
union {
|
|
struct rsu_tx_radiotap_header th;
|
|
uint8_t pad[64];
|
|
} sc_txtapu;
|
|
#define sc_txtap sc_txtapu.th
|
|
int sc_txtap_len;
|
|
};
|