bc198428ea
we call an platform dependant topo function as well as clean up all the XLR specific ifdefs around smp platform init. Obtained from: JC
583 lines
15 KiB
C
583 lines
15 KiB
C
/*-
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* Copyright (c) 2006-2009 RMI Corporation
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* Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/rtprio.h>
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#include <sys/systm.h>
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#include <sys/interrupt.h>
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#include <sys/limits.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/random.h>
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#include <sys/cons.h> /* cinit() */
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <sys/queue.h>
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#include <sys/smp.h>
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#include <sys/timetc.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuinfo.h>
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#include <machine/cpuregs.h>
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#include <machine/frame.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/asm.h>
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#include <machine/pmap.h>
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#include <machine/trap.h>
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#include <machine/clock.h>
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#include <machine/fls64.h>
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#include <machine/intr_machdep.h>
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#include <machine/smp.h>
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#include <mips/rmi/rmi_mips_exts.h>
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#include <mips/rmi/iomap.h>
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#include <mips/rmi/clock.h>
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#include <mips/rmi/msgring.h>
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#include <mips/rmi/xlrconfig.h>
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#include <mips/rmi/interrupt.h>
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#include <mips/rmi/pic.h>
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#ifdef XLR_PERFMON
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#include <mips/rmi/perfmon.h>
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#endif
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void mpwait(void);
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void enable_msgring_int(void *arg);
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unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE);
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/* 4KB static data aread to keep a copy of the bootload env until
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the dynamic kenv is setup */
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char boot1_env[4096];
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int rmi_spin_mutex_safe=0;
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/*
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* Parameters from boot loader
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*/
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struct boot1_info xlr_boot1_info;
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struct xlr_loader_info xlr_loader_info; /* FIXME : Unused */
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int xlr_run_mode;
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int xlr_argc;
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char **xlr_argv, **xlr_envp;
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uint64_t cpu_mask_info;
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uint32_t xlr_online_cpumask;
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uint32_t xlr_core_cpu_mask = 0x1; /* Core 0 thread 0 is always there */
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void
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platform_reset(void)
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{
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/* FIXME : use proper define */
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u_int32_t *mmio = (u_int32_t *) 0xbef18000;
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printf("Rebooting the system now\n");
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mmio[8] = 0x1;
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}
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int xlr_asid_pcpu = 256; /* This the default */
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int xlr_shtlb_enabled = 0;
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/* This function sets up the number of tlb entries available
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to the kernel based on the number of threads brought up.
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The ASID range also gets divided similarly.
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THE NUMBER OF THREADS BROUGHT UP IN EACH CORE MUST BE THE SAME
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NOTE: This function will mark all 64TLB entries as available
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to the threads brought up in the core. If kernel is brought with say mask
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0x33333333, no TLBs will be available to the threads in each core.
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*/
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static void
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setup_tlb_resource(void)
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{
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int mmu_setup;
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int value = 0;
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uint32_t cpu_map = xlr_boot1_info.cpu_online_map;
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uint32_t thr_mask = cpu_map >> (xlr_core_id() << 2);
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uint8_t core0 = xlr_boot1_info.cpu_online_map & 0xf;
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uint8_t core_thr_mask;
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int i = 0, count = 0;
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/* If CPU0 did not enable shared TLB, other cores need to follow */
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if ((xlr_core_id() != 0) && (xlr_shtlb_enabled == 0))
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return;
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/* First check if each core is brought up with the same mask */
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for (i = 1; i < 8; i++) {
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core_thr_mask = cpu_map >> (i << 2);
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core_thr_mask &= 0xf;
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if (core_thr_mask && core_thr_mask != core0) {
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printf
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("Each core must be brought with same cpu mask\n");
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printf("Cannot enabled shared TLB. ");
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printf("Falling back to split TLB mode\n");
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return;
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}
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}
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xlr_shtlb_enabled = 1;
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for (i = 0; i < 4; i++)
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if (thr_mask & (1 << i))
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count++;
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switch (count) {
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case 1:
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xlr_asid_pcpu = 256;
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break;
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case 2:
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xlr_asid_pcpu = 128;
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value = 0x2;
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break;
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default:
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xlr_asid_pcpu = 64;
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value = 0x3;
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break;
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}
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mmu_setup = read_32bit_phnx_ctrl_reg(4, 0);
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mmu_setup = mmu_setup & ~0x06;
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mmu_setup |= (value << 1);
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/* turn on global mode */
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#ifndef SMP
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mmu_setup |= 0x01;
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#endif
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write_32bit_phnx_ctrl_reg(4, 0, mmu_setup);
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}
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/*
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* Platform specific register setup for CPUs
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* XLR has control registers accessible with MFCR/MTCR instructions, this
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* code initialized them from the environment variable xlr.cr of form:
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* xlr.cr=reg:val[,reg:val]*, all values in hex.
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* To enable shared TLB option use xlr.shtlb=1
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*/
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void
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platform_cpu_init()
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{
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char *hw_env;
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char *start, *end;
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uint32_t reg, val;
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int thr_id = xlr_thr_id();
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/*
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* XXX: SMP now need different wired mappings for threads
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* we cannot share TLBs.
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*/
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if (thr_id == 0) {
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if ((hw_env = getenv("xlr.shtlb")) != NULL) {
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start = hw_env;
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reg = strtoul(start, &end, 16);
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if (start != end && reg != 0)
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setup_tlb_resource();
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} else {
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/* By default TLB entries are shared in a core */
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setup_tlb_resource();
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}
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}
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if ((hw_env = getenv("xlr.cr")) == NULL)
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return;
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start = hw_env;
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while (*start != '\0') {
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reg = strtoul(start, &end, 16);
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if (start == end) {
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printf("Invalid value in xlr.cr %s, cannot read a hex value at %d\n",
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hw_env, start - hw_env);
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goto err_return;
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}
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if (*end != ':') {
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printf("Invalid format in xlr.cr %s, ':' expected at pos %d\n",
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hw_env, end - hw_env);
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goto err_return;
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}
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start = end + 1;/* step over ':' */
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val = strtoul(start, &end, 16);
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if (start == end) {
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printf("Invalid value in xlr.cr %s, cannot read a hex value at pos %d\n",
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hw_env, start - hw_env);
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goto err_return;
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}
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if (*end != ',' && *end != '\0') {
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printf("Invalid format in xlr.cr %s, ',' expected at pos %d\n",
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hw_env, end - hw_env);
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goto err_return;
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}
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xlr_mtcr(reg, val);
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if (*end == ',')
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start = end + 1; /* skip over ',' */
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else
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start = end;
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}
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freeenv(hw_env);
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return;
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err_return:
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panic("Invalid xlr.cr setting!");
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return;
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}
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static void
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xlr_set_boot_flags(void)
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{
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char *p;
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for (p = getenv("boot_flags"); p && *p != '\0'; p++) {
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switch (*p) {
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case 'd':
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case 'D':
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boothowto |= RB_KDB;
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break;
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case 'g':
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case 'G':
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boothowto |= RB_GDB;
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break;
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case 'v':
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case 'V':
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boothowto |= RB_VERBOSE;
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break;
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case 's': /* single-user (default, supported for sanity) */
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case 'S':
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boothowto |= RB_SINGLE;
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break;
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default:
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printf("Unrecognized boot flag '%c'.\n", *p);
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break;
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}
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}
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if (p)
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freeenv(p);
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return;
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}
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extern uint32_t _end;
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static void
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mips_init(void)
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{
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init_param1();
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init_param2(physmem);
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/* XXX: Catch 22. Something touches the tlb. */
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mips_cpu_init();
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pmap_bootstrap();
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#ifdef DDB
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kdb_init();
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if (boothowto & RB_KDB) {
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kdb_enter("Boot flags requested debugger", NULL);
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}
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#endif
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mips_proc0_init();
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write_c0_register32(MIPS_COP_0_OSSCRATCH, 7, pcpup->pc_curthread);
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mutex_init();
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}
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void
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platform_start(__register_t a0 __unused,
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__register_t a1 __unused,
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__register_t a2 __unused,
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__register_t a3 __unused)
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{
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vm_size_t physsz = 0;
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int i, j;
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struct xlr_boot1_mem_map *boot_map;
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#ifdef SMP
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uint32_t tmp;
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void (*wakeup) (void *, void *, unsigned int);
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#endif
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/* XXX no zeroing of BSS? */
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/* Initialize pcpu stuff */
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mips_pcpu0_init();
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/* XXX FIXME the code below is not 64 bit clean */
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/* Save boot loader and other stuff from scratch regs */
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xlr_boot1_info = *(struct boot1_info *)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0);
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cpu_mask_info = read_c0_register64(MIPS_COP_0_OSSCRATCH, 1);
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xlr_online_cpumask = read_c0_register32(MIPS_COP_0_OSSCRATCH, 2);
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xlr_run_mode = read_c0_register32(MIPS_COP_0_OSSCRATCH, 3);
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xlr_argc = read_c0_register32(MIPS_COP_0_OSSCRATCH, 4);
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xlr_argv = (char **)read_c0_register32(MIPS_COP_0_OSSCRATCH, 5);
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xlr_envp = (char **)read_c0_register32(MIPS_COP_0_OSSCRATCH, 6);
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/* TODO: Verify the magic number here */
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/* FIXMELATER: xlr_boot1_info.magic_number */
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/* initialize console so that we have printf */
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boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
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/* clockrate used by delay, so initialize it here */
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cpu_clock = xlr_boot1_info.cpu_frequency / 1000000;
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/*
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* Note the time counter on CPU0 runs not at system clock speed, but
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* at PIC time counter speed (which is returned by
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* platform_get_frequency(). Thus we do not use
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* xlr_boot1_info.cpu_frequency here.
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*/
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mips_timer_early_init(platform_get_frequency());
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/* Init the time counter in the PIC and local putc routine*/
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rmi_early_counter_init();
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/* Init console please */
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cninit();
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init_static_kenv(boot1_env, sizeof(boot1_env));
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printf("Environment (from %d args):\n", xlr_argc - 1);
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if (xlr_argc == 1)
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printf("\tNone\n");
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for (i = 1; i < xlr_argc; i++) {
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char *n;
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printf("\t%s\n", xlr_argv[i]);
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n = strsep(&xlr_argv[i], "=");
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if (xlr_argv[i] == NULL)
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setenv(n, "1");
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else
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setenv(n, xlr_argv[i]);
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}
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xlr_set_boot_flags();
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/* get physical memory info from boot loader */
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boot_map = (struct xlr_boot1_mem_map *)
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(unsigned long)xlr_boot1_info.psb_mem_map;
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for (i = 0, j = 0; i < boot_map->num_entries; i++, j += 2) {
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if (boot_map->physmem_map[i].type == BOOT1_MEM_RAM) {
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if (j == 14) {
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printf("*** ERROR *** memory map too large ***\n");
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break;
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}
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if (j == 0) {
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/* TODO FIXME */
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/* start after kernel end */
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phys_avail[0] = (vm_paddr_t)
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MIPS_KSEG0_TO_PHYS(&_end) + 0x20000;
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/* boot loader start */
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/* HACK to Use bootloaders memory region */
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/* TODO FIXME */
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if (boot_map->physmem_map[0].size == 0x0c000000) {
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boot_map->physmem_map[0].size = 0x0ff00000;
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}
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phys_avail[1] = boot_map->physmem_map[0].addr +
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boot_map->physmem_map[0].size;
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printf("First segment: addr:%p -> %p \n",
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(void *)phys_avail[0],
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(void *)phys_avail[1]);
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} else {
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/*
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* Can't use this code yet, because most of the fixed allocations happen from
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* the biggest physical area. If we have more than 512M memory the kernel will try
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* to map from the second are which is not in KSEG0 and not mapped
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*/
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phys_avail[j] = (vm_paddr_t)
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boot_map->physmem_map[i].addr;
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phys_avail[j + 1] = phys_avail[j] +
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boot_map->physmem_map[i].size;
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if (phys_avail[j + 1] < phys_avail[j] ) {
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/* Houston we have an issue. Memory is
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* larger than possible. Its probably in
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* 64 bit > 4Gig and we are in 32 bit mode.
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*/
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phys_avail[j + 1] = 0xfffff000;
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printf("boot map size was %llx\n", boot_map->physmem_map[i].size);
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boot_map->physmem_map[i].size = phys_avail[j + 1] - phys_avail[j];
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printf("reduced to %llx\n", boot_map->physmem_map[i].size);
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}
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printf("Next segment : addr:%p -> %p \n",
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(void *)phys_avail[j],
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(void *)phys_avail[j+1]);
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}
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physsz += boot_map->physmem_map[i].size;
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}
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}
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/* FIXME XLR TODO */
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phys_avail[j] = phys_avail[j + 1] = 0;
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realmem = physmem = btoc(physsz);
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/* Store pcpu in scratch 5 */
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write_c0_register32(MIPS_COP_0_OSSCRATCH, 5, pcpup);
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/* Set up hz, among others. */
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mips_init();
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#ifdef SMP
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/*
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* If thread 0 of any core is not available then mark whole core as
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* not available
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*/
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tmp = xlr_boot1_info.cpu_online_map;
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for (i = 4; i < MAXCPU; i += 4) {
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if ((tmp & (0xf << i)) && !(tmp & (0x1 << i))) {
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/*
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* Oopps.. thread 0 is not available. Disable whole
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* core
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*/
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tmp = tmp & ~(0xf << i);
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printf("WARNING: Core %d is disabled because thread 0"
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" of this core is not enabled.\n", i / 4);
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}
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}
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xlr_boot1_info.cpu_online_map = tmp;
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/* Wakeup Other cpus, and put them in bsd park code. */
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for (i = 1, j = 1; i < 32; i++) {
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/* Allocate stack for all other cpus from fbsd kseg0 memory. */
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if ((1U << i) & xlr_boot1_info.cpu_online_map) {
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if ((i & 0x3) == 0) /* store thread0 of each core */
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xlr_core_cpu_mask |= (1 << j);
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j++;
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}
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}
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wakeup = ((void (*) (void *, void *, unsigned int))
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(unsigned long)(xlr_boot1_info.wakeup));
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printf("Waking up CPUs 0x%llx.\n", xlr_boot1_info.cpu_online_map & ~(0x1U));
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if (xlr_boot1_info.cpu_online_map & ~(0x1U))
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wakeup(mpwait, 0,
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(unsigned int)xlr_boot1_info.cpu_online_map);
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#endif
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/* xlr specific post initialization */
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/*
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|
* The expectation is that mutex_init() is already done in
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* mips_init() XXX NOTE: We may need to move this to SMP based init
|
|
* code for each CPU, later.
|
|
*/
|
|
rmi_spin_mutex_safe = 1;
|
|
on_chip_init();
|
|
mips_timer_init_params(platform_get_frequency(), 0);
|
|
printf("Platform specific startup now completes\n");
|
|
}
|
|
|
|
void
|
|
platform_identify(void)
|
|
{
|
|
printf("Board [%d:%d], processor 0x%08x\n", (int)xlr_boot1_info.board_major_version,
|
|
(int)xlr_boot1_info.board_minor_version, mips_rd_prid());
|
|
|
|
|
|
}
|
|
|
|
/*
|
|
* XXX Maybe return the state of the watchdog in enter, and pass it to
|
|
* exit? Like spl().
|
|
*/
|
|
void
|
|
platform_trap_enter(void)
|
|
{
|
|
}
|
|
|
|
void
|
|
platform_trap_exit(void)
|
|
{
|
|
}
|
|
|
|
#ifdef SMP
|
|
int xlr_ap_release[MAXCPU];
|
|
|
|
int platform_start_ap(int cpuid)
|
|
{
|
|
/*
|
|
* other cpus are enabled by the boot loader and they will be
|
|
* already looping in mpwait, release them
|
|
*/
|
|
atomic_store_rel_int(&xlr_ap_release[cpuid], 1);
|
|
return 0;
|
|
}
|
|
|
|
void platform_init_ap(int processor_id)
|
|
{
|
|
uint32_t stat;
|
|
|
|
/* Setup interrupts for secondary CPUs here */
|
|
stat = mips_rd_status();
|
|
KASSERT((stat & MIPS_SR_INT_IE) == 0,
|
|
("Interrupts enabled in %s!", __func__));
|
|
stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
|
|
mips_wr_status(stat);
|
|
|
|
xlr_unmask_hard_irq((void *)platform_ipi_intrnum());
|
|
xlr_unmask_hard_irq((void *)IRQ_TIMER);
|
|
if (xlr_thr_id() == 0) {
|
|
xlr_msgring_cpu_init();
|
|
xlr_unmask_hard_irq((void *)IRQ_MSGRING);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
int platform_ipi_intrnum(void)
|
|
{
|
|
return IRQ_IPI;
|
|
}
|
|
|
|
void platform_ipi_send(int cpuid)
|
|
{
|
|
pic_send_ipi(cpuid, platform_ipi_intrnum(), 0);
|
|
}
|
|
|
|
void platform_ipi_clear(void)
|
|
{
|
|
}
|
|
|
|
int platform_processor_id(void)
|
|
{
|
|
return xlr_cpu_id();
|
|
}
|
|
|
|
int platform_num_processors(void)
|
|
{
|
|
return fls(xlr_boot1_info.cpu_online_map);
|
|
}
|
|
|
|
struct cpu_group *
|
|
platform_smp_topo()
|
|
{
|
|
return (smp_topo_2level(CG_SHARE_L2, platform_num_processors() / 4,
|
|
CG_SHARE_L1, 4, CG_FLAG_THREAD));
|
|
}
|
|
#endif
|