bc88bb2bf3
Family-common and CPU-specific counters implemented. Supported CPUs: ARM Cortex A53/57/72. Reviewed by: andrew, bz, emaste, gnn, jhb Sponsored by: ARM Limited Differential Revision: https://reviews.freebsd.org/D2555
234 lines
8.3 KiB
C
234 lines
8.3 KiB
C
/*-
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* Copyright (c) 2013, 2014 Andrew Turner
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* Copyright (c) 2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Andrew Turner under
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* sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ARMREG_H_
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#define _MACHINE_ARMREG_H_
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#define READ_SPECIALREG(reg) \
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({ uint64_t val; \
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__asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \
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val; \
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})
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#define WRITE_SPECIALREG(reg, val) \
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__asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val))
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/* CPACR_EL1 */
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#define CPACR_FPEN_MASK (0x3 << 20)
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#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */
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#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */
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#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */
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#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */
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#define CPACR_TTA (0x1 << 28)
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/* CTR_EL0 - Cache Type Register */
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#define CTR_DLINE_SHIFT 16
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#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)
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#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
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#define CTR_ILINE_SHIFT 0
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#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)
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#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
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/* ESR_ELx */
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#define ESR_ELx_ISS_MASK 0x00ffffff
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#define ISS_INSN_FnV (0x01 << 10)
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#define ISS_INSN_EA (0x01 << 9)
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#define ISS_INSN_S1PTW (0x01 << 7)
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#define ISS_INSN_IFSC_MASK (0x1f << 0)
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#define ISS_DATA_ISV (0x01 << 24)
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#define ISS_DATA_SAS_MASK (0x03 << 22)
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#define ISS_DATA_SSE (0x01 << 21)
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#define ISS_DATA_SRT_MASK (0x1f << 16)
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#define ISS_DATA_SF (0x01 << 15)
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#define ISS_DATA_AR (0x01 << 14)
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#define ISS_DATA_FnV (0x01 << 10)
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#define ISS_DATa_EA (0x01 << 9)
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#define ISS_DATa_CM (0x01 << 8)
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#define ISS_INSN_S1PTW (0x01 << 7)
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#define ISS_DATa_WnR (0x01 << 6)
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#define ISS_DATA_DFSC_MASK (0x1f << 0)
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#define ESR_ELx_IL (0x01 << 25)
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#define ESR_ELx_EC_SHIFT 26
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#define ESR_ELx_EC_MASK (0x3f << 26)
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#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
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#define EXCP_UNKNOWN 0x00 /* Unkwn exception */
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#define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */
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#define EXCP_ILL_STATE 0x0e /* Illegal execution state */
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#define EXCP_SVC 0x15 /* SVC trap */
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#define EXCP_MSR 0x18 /* MSR/MRS trap */
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#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */
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#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */
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#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */
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#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */
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#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */
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#define EXCP_SP_ALIGN 0x26 /* SP slignment fault */
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#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */
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#define EXCP_SERROR 0x2f /* SError interrupt */
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#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */
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#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */
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#define EXCP_BRK 0x3c /* Breakpoint */
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/* ICC_CTLR_EL1 */
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#define ICC_CTLR_EL1_EOIMODE (1U << 1)
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/* ICC_IAR1_EL1 */
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#define ICC_IAR1_EL1_SPUR (0x03ff)
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/* ICC_IGRPEN0_EL1 */
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#define ICC_IGRPEN0_EL1_EN (1U << 0)
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/* ICC_PMR_EL1 */
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#define ICC_PMR_EL1_PRIO_MASK (0xFFUL)
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/* ICC_SRE_EL1 */
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#define ICC_SRE_EL1_SRE (1U << 0)
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/* ICC_SRE_EL2 */
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#define ICC_SRE_EL2_EN (1U << 3)
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/* ID_AA64PFR0_EL1 */
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#define ID_AA64PFR0_EL0_MASK (0xf << 0)
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#define ID_AA64PFR0_EL1_MASK (0xf << 4)
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#define ID_AA64PFR0_EL2_MASK (0xf << 8)
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#define ID_AA64PFR0_EL3_MASK (0xf << 12)
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#define ID_AA64PFR0_FP_MASK (0xf << 16)
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#define ID_AA64PFR0_FP_IMPL (0x0 << 16) /* Floating-point implemented */
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#define ID_AA64PFR0_FP_NONE (0xf << 16) /* Floating-point not implemented */
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#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << 20)
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#define ID_AA64PFR0_GIC_SHIFT (24)
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#define ID_AA64PFR0_GIC_BITS (0x4) /* Number of bits in GIC field */
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#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT)
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#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT)
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/* MAIR_EL1 - Memory Attribute Indirection Register */
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#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
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#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
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/* SCTLR_EL1 - System Control Register */
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#define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */
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#define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */
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#define SCTLR_M 0x00000001
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#define SCTLR_A 0x00000002
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#define SCTLR_C 0x00000004
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#define SCTLR_SA 0x00000008
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#define SCTLR_SA0 0x00000010
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#define SCTLR_CP15BEN 0x00000020
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#define SCTLR_THEE 0x00000040
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#define SCTLR_ITD 0x00000080
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#define SCTLR_SED 0x00000100
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#define SCTLR_UMA 0x00000200
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#define SCTLR_I 0x00001000
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#define SCTLR_DZE 0x00004000
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#define SCTLR_UCT 0x00008000
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#define SCTLR_nTWI 0x00010000
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#define SCTLR_nTWE 0x00040000
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#define SCTLR_WXN 0x00080000
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#define SCTLR_EOE 0x01000000
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#define SCTLR_EE 0x02000000
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#define SCTLR_UCI 0x04000000
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/* SPSR_EL1 */
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/*
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* When the exception is taken in AArch64:
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* M[4] is 0 for AArch64 mode
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* M[3:2] is the exception level
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* M[1] is unused
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* M[0] is the SP select:
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* 0: always SP0
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* 1: current ELs SP
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*/
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#define PSR_M_EL0t 0x00000000
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#define PSR_M_EL1t 0x00000004
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#define PSR_M_EL1h 0x00000005
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#define PSR_M_EL2t 0x00000008
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#define PSR_M_EL2h 0x00000009
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#define PSR_M_MASK 0x0000001f
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#define PSR_F 0x00000040
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#define PSR_I 0x00000080
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#define PSR_A 0x00000100
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#define PSR_D 0x00000200
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#define PSR_IL 0x00100000
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#define PSR_SS 0x00200000
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#define PSR_V 0x10000000
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#define PSR_C 0x20000000
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#define PSR_Z 0x40000000
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#define PSR_N 0x80000000
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/* TCR_EL1 - Translation Control Register */
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#define TCR_ASID_16 (1 << 36)
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#define TCR_IPS_SHIFT 32
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#define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT)
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#define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT)
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#define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT)
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#define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT)
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#define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT)
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#define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT)
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#define TCR_TG1_SHIFT 30
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#define TCR_TG1_16K (1 << TCR_TG1_SHIFT)
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#define TCR_TG1_4K (2 << TCR_TG1_SHIFT)
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#define TCR_TG1_64K (3 << TCR_TG1_SHIFT)
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#define TCR_T1SZ_SHIFT 16
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#define TCR_T0SZ_SHIFT 0
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#define TCR_TxSZ(x) (((x) << TCR_T1SZ_SHIFT) | ((x) << TCR_T0SZ_SHIFT))
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/* Saved Program Status Register */
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#define DBG_SPSR_SS (0x1 << 21)
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/* Monitor Debug System Control Register */
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#define DBG_MDSCR_SS (0x1 << 0)
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#define DBG_MDSCR_KDE (0x1 << 13)
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#define DBG_MDSCR_MDE (0x1 << 15)
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/* Perfomance Monitoring Counters */
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#define PMCR_E (1 << 0) /* Enable all counters */
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#define PMCR_P (1 << 1) /* Reset all counters */
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#define PMCR_C (1 << 2) /* Clock counter reset */
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#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */
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#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
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#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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#define PMCR_LC (1 << 6) /* Long cycle count enable */
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#define PMCR_IMP_SHIFT 24 /* Implementer code */
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#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
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#define PMCR_IDCODE_SHIFT 16 /* Identification code */
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#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
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#define PMCR_IDCODE_CORTEX_A57 0x01
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#define PMCR_IDCODE_CORTEX_A72 0x02
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#define PMCR_IDCODE_CORTEX_A53 0x03
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#define PMCR_N_SHIFT 11 /* Number of counters implemented */
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#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
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#endif /* !_MACHINE_ARMREG_H_ */
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