4290b4b849
The QorIQ SoCs don't actually support multicast interrupts, and the references state explicitly that multicast is undefined behavior. Avoid the undefined behavior by binding to only a single CPU, using a quirk to determine if this is necessary. MFC after: 3 weeks
94 lines
2.9 KiB
C
94 lines
2.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (C) 2002 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _POWERPC_OPENPICVAR_H_
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#define _POWERPC_OPENPICVAR_H_
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#define OPENPIC_DEVSTR "OpenPIC Interrupt Controller"
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#define OPENPIC_IRQMAX 256 /* h/w allows more */
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#define OPENPIC_QUIRK_SINGLE_BIND 1 /* Bind interrupts to only 1 CPU */
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/* Names match the macros in openpicreg.h. */
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struct openpic_timer {
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uint32_t tcnt;
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uint32_t tbase;
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uint32_t tvec;
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uint32_t tdst;
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};
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struct openpic_softc {
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device_t sc_dev;
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struct resource *sc_memr;
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struct resource *sc_intr;
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bus_space_tag_t sc_bt;
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bus_space_handle_t sc_bh;
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char *sc_version;
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int sc_rid;
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int sc_irq;
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void *sc_icookie;
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u_int sc_ncpu;
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u_int sc_nirq;
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int sc_psim;
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u_int sc_quirks;
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/* Saved states. */
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uint32_t sc_saved_config;
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uint32_t sc_saved_ipis[4];
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uint32_t sc_saved_prios[4];
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struct openpic_timer sc_saved_timers[OPENPIC_TIMERS];
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uint32_t sc_saved_vectors[OPENPIC_SRC_VECTOR_COUNT];
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};
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extern devclass_t openpic_devclass;
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/*
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* Bus-independent attach i/f
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*/
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int openpic_common_attach(device_t, uint32_t);
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/*
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* PIC interface.
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*/
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void openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **);
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void openpic_config(device_t, u_int, enum intr_trigger, enum intr_polarity);
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void openpic_dispatch(device_t, struct trapframe *);
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void openpic_enable(device_t, u_int, u_int, void **);
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void openpic_eoi(device_t, u_int, void *);
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void openpic_ipi(device_t, u_int);
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void openpic_mask(device_t, u_int, void *);
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void openpic_unmask(device_t, u_int, void *);
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int openpic_suspend(device_t dev);
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int openpic_resume(device_t dev);
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#endif /* _POWERPC_OPENPICVAR_H_ */
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