100 lines
3.8 KiB
Diff
100 lines
3.8 KiB
Diff
Pull in r198281 from upstream llvm trunk (by Venkatraman Govindaraju):
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[SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order.
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Introduced here: http://svnweb.freebsd.org/changeset/base/262261
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Index: lib/Target/Sparc/SparcISelLowering.cpp
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===================================================================
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--- lib/Target/Sparc/SparcISelLowering.cpp
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+++ lib/Target/Sparc/SparcISelLowering.cpp
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@@ -1525,6 +1525,9 @@ SparcTargetLowering::SparcTargetLowering(TargetMac
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setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::MULHU, MVT::i64, Expand);
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setOperationAction(ISD::MULHS, MVT::i64, Expand);
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+
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+ setOperationAction(ISD::UMULO, MVT::i64, Custom);
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+ setOperationAction(ISD::SMULO, MVT::i64, Custom);
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}
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex.
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@@ -2673,6 +2676,53 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op
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return DAG.getMergeValues(Ops, 2, dl);
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}
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+// Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
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+// in LegalizeDAG.cpp except the order of arguments to the library function.
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+static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
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+ const SparcTargetLowering &TLI)
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+{
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+ unsigned opcode = Op.getOpcode();
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+ assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
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+
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+ bool isSigned = (opcode == ISD::SMULO);
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+ EVT VT = MVT::i64;
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+ EVT WideVT = MVT::i128;
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+ SDLoc dl(Op);
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+ SDValue LHS = Op.getOperand(0);
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+
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+ if (LHS.getValueType() != VT)
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+ return Op;
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+
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+ SDValue ShiftAmt = DAG.getConstant(63, VT);
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+
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+ SDValue RHS = Op.getOperand(1);
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+ SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
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+ SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
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+ SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
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+
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+ SDValue MulResult = TLI.makeLibCall(DAG,
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+ RTLIB::MUL_I128, WideVT,
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+ Args, 4, isSigned, dl).first;
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+ SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
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+ MulResult, DAG.getIntPtrConstant(0));
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+ SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
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+ MulResult, DAG.getIntPtrConstant(1));
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+ if (isSigned) {
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+ SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
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+ TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
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+ } else {
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+ TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT),
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+ ISD::SETNE);
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+ }
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+ // MulResult is a node with an illegal type. Because such things are not
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+ // generally permitted during this phase of legalization, delete the
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+ // node. The above EXTRACT_ELEMENT nodes should have been folded.
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+ DAG.DeleteNode(MulResult.getNode());
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+
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+ SDValue Ops[2] = { BottomHalf, TopHalf } ;
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+ return DAG.getMergeValues(Ops, 2, dl);
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+}
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+
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SDValue SparcTargetLowering::
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LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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@@ -2726,6 +2776,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) cons
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case ISD::ADDE:
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case ISD::SUBC:
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case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
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+ case ISD::UMULO:
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+ case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
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}
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}
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Index: test/CodeGen/SPARC/64cond.ll
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===================================================================
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--- test/CodeGen/SPARC/64cond.ll
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+++ test/CodeGen/SPARC/64cond.ll
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@@ -111,6 +111,11 @@ entry:
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}
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; CHECK-LABEL: setcc_resultty
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+; CHECK-DAG: srax %i0, 63, %o0
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+; CHECK-DAG: or %g0, %i0, %o1
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+; CHECK-DAG: or %g0, 0, %o2
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+; CHECK-DAG: or %g0, 32, %o3
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+; CHECK-DAG: call __multi3
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; CHECK: cmp
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; CHECK: movne %xcc, 1, [[R:%[gilo][0-7]]]
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; CHECK: or [[R]], %i1, %i0
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