a426b286c8
patch for r263619, and unify all the URLs to point to svnweb.
56 lines
2.2 KiB
Diff
56 lines
2.2 KiB
Diff
Pull in r199786 from upstream llvm trunk (by Venkatraman Govindaraju):
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[Sparc] Add support for inline assembly constraints which specify registers by their aliases.
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Introduced here: http://svnweb.freebsd.org/changeset/base/262261
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Index: lib/Target/Sparc/SparcISelLowering.cpp
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===================================================================
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--- lib/Target/Sparc/SparcISelLowering.cpp
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+++ lib/Target/Sparc/SparcISelLowering.cpp
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@@ -2992,6 +2992,26 @@ SparcTargetLowering::getRegForInlineAsmConstraint(
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case 'r':
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return std::make_pair(0U, &SP::IntRegsRegClass);
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}
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+ } else if (!Constraint.empty() && Constraint.size() <= 5
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+ && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
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+ // constraint = '{r<d>}'
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+ // Remove the braces from around the name.
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+ StringRef name(Constraint.data()+1, Constraint.size()-2);
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+ // Handle register aliases:
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+ // r0-r7 -> g0-g7
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+ // r8-r15 -> o0-o7
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+ // r16-r23 -> l0-l7
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+ // r24-r31 -> i0-i7
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+ uint64_t intVal = 0;
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+ if (name.substr(0, 1).equals("r")
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+ && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
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+ const char regTypes[] = { 'g', 'o', 'l', 'i' };
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+ char regType = regTypes[intVal/8];
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+ char regIdx = '0' + (intVal % 8);
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+ char tmp[] = { '{', regType, regIdx, '}', 0 };
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+ std::string newConstraint = std::string(tmp);
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+ return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT);
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+ }
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}
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return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
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Index: test/CodeGen/SPARC/inlineasm.ll
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===================================================================
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--- test/CodeGen/SPARC/inlineasm.ll
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+++ test/CodeGen/SPARC/inlineasm.ll
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@@ -33,3 +33,13 @@ entry:
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%0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)
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ret i32 %0
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}
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+
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+; CHECK-LABEL: test_constraint_reg
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+; CHECK: ldda [%o1] 43, %g2
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+; CHECK: ldda [%o1] 43, %g3
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+define void @test_constraint_reg(i32 %s, i32* %ptr) {
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+entry:
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+ %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43)
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+ %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g3},r,n"(i32* %ptr, i32 43)
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+ ret void
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+}
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