51369649b0
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266 lines
7.6 KiB
C
266 lines
7.6 KiB
C
/* $NetBSD: fpu_explode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93
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*/
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/*
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* FPU subroutines: `explode' the machine's `packed binary' format numbers
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* into our internal format.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <machine/fpu.h>
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#include <machine/ieee.h>
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#include <machine/pcb.h>
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#include <powerpc/fpu/fpu_arith.h>
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#include <powerpc/fpu/fpu_emu.h>
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#include <powerpc/fpu/fpu_extern.h>
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#include <powerpc/fpu/fpu_instr.h>
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/*
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* N.B.: in all of the following, we assume the FP format is
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*
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* ---------------------------
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* | s | exponent | fraction |
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* ---------------------------
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*
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* (which represents -1**s * 1.fraction * 2**exponent), so that the
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* sign bit is way at the top (bit 31), the exponent is next, and
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* then the remaining bits mark the fraction. A zero exponent means
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* zero or denormalized (0.fraction rather than 1.fraction), and the
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* maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
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*
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* Since the sign bit is always the topmost bit---this holds even for
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* integers---we set that outside all the *tof functions. Each function
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* returns the class code for the new number (but note that we use
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* FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
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*/
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/*
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* int -> fpn.
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*/
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int
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fpu_itof(struct fpn *fp, u_int i)
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{
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if (i == 0)
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return (FPC_ZERO);
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/*
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* The value FP_1 represents 2^FP_LG, so set the exponent
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* there and let normalization fix it up. Convert negative
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* numbers to sign-and-magnitude. Note that this relies on
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* fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
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*/
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fp->fp_exp = FP_LG;
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fp->fp_mant[0] = (int)i < 0 ? -i : i;
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fp->fp_mant[1] = 0;
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fp->fp_mant[2] = 0;
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fp->fp_mant[3] = 0;
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fpu_norm(fp);
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return (FPC_NUM);
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}
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/*
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* 64-bit int -> fpn.
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*/
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int
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fpu_xtof(struct fpn *fp, u_int64_t i)
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{
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if (i == 0)
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return (FPC_ZERO);
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/*
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* The value FP_1 represents 2^FP_LG, so set the exponent
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* there and let normalization fix it up. Convert negative
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* numbers to sign-and-magnitude. Note that this relies on
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* fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
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*/
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fp->fp_exp = FP_LG2;
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*((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i;
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fp->fp_mant[2] = 0;
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fp->fp_mant[3] = 0;
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fpu_norm(fp);
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return (FPC_NUM);
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}
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#define mask(nbits) ((1L << (nbits)) - 1)
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/*
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* All external floating formats convert to internal in the same manner,
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* as defined here. Note that only normals get an implied 1.0 inserted.
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*/
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#define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
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if (exp == 0) { \
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if (allfrac == 0) \
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return (FPC_ZERO); \
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fp->fp_exp = 1 - expbias; \
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fp->fp_mant[0] = f0; \
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fp->fp_mant[1] = f1; \
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fp->fp_mant[2] = f2; \
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fp->fp_mant[3] = f3; \
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fpu_norm(fp); \
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return (FPC_NUM); \
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} \
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if (exp == (2 * expbias + 1)) { \
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if (allfrac == 0) \
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return (FPC_INF); \
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fp->fp_mant[0] = f0; \
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fp->fp_mant[1] = f1; \
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fp->fp_mant[2] = f2; \
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fp->fp_mant[3] = f3; \
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return (FPC_QNAN); \
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} \
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fp->fp_exp = exp - expbias; \
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fp->fp_mant[0] = FP_1 | f0; \
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fp->fp_mant[1] = f1; \
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fp->fp_mant[2] = f2; \
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fp->fp_mant[3] = f3; \
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return (FPC_NUM)
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/*
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* 32-bit single precision -> fpn.
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* We assume a single occupies at most (64-FP_LG) bits in the internal
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* format: i.e., needs at most fp_mant[0] and fp_mant[1].
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*/
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int
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fpu_stof(struct fpn *fp, u_int i)
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{
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int exp;
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u_int frac, f0, f1;
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#define SNG_SHIFT (SNG_FRACBITS - FP_LG)
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exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
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frac = i & mask(SNG_FRACBITS);
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f0 = frac >> SNG_SHIFT;
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f1 = frac << (32 - SNG_SHIFT);
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FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
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}
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/*
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* 64-bit double -> fpn.
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* We assume this uses at most (96-FP_LG) bits.
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*/
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int
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fpu_dtof(struct fpn *fp, u_int i, u_int j)
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{
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int exp;
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u_int frac, f0, f1, f2;
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#define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
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exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
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frac = i & mask(DBL_FRACBITS - 32);
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f0 = frac >> DBL_SHIFT;
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f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
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f2 = j << (32 - DBL_SHIFT);
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frac |= j;
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FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
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}
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/*
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* Explode the contents of a register / regpair / regquad.
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* If the input is a signalling NaN, an NV (invalid) exception
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* will be set. (Note that nothing but NV can occur until ALU
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* operations are performed.)
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*/
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void
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fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)
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{
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u_int s, *space;
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u_int64_t l, *xspace;
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xspace = (u_int64_t *)&fe->fe_fpstate->fpr[reg].fpr;
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l = xspace[0];
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space = (u_int *)&fe->fe_fpstate->fpr[reg].fpr;
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s = space[0];
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fp->fp_sign = s >> 31;
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fp->fp_sticky = 0;
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switch (type) {
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case FTYPE_LNG:
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s = fpu_xtof(fp, l);
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break;
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case FTYPE_INT:
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s = fpu_itof(fp, space[1]);
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break;
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case FTYPE_SNG:
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s = fpu_stof(fp, s);
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break;
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case FTYPE_DBL:
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s = fpu_dtof(fp, s, space[1]);
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break;
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default:
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panic("fpu_explode");
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panic("fpu_explode: invalid type %d", type);
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}
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if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
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/*
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* Input is a signalling NaN. All operations that return
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* an input NaN operand put it through a ``NaN conversion'',
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* which basically just means ``turn on the quiet bit''.
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* We do this here so that all NaNs internally look quiet
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* (we can tell signalling ones by their class).
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*/
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fp->fp_mant[0] |= FP_QUIETBIT;
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fe->fe_cx = FPSCR_VXSNAN; /* assert invalid operand */
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s = FPC_SNAN;
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}
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fp->fp_class = s;
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DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
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((type == FTYPE_INT) ? 'i' :
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((type == FTYPE_SNG) ? 's' :
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((type == FTYPE_DBL) ? 'd' : '?'))),
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reg));
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DUMPFPN(FPE_REG, fp);
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DPRINTF(FPE_REG, ("\n"));
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}
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