ef6da5e5c7
Summary: POWER9 systems use a new interrupt controller, XIVE, managed through OPAL firmware calls. The OPAL firmware includes support for emulating the previous generation XICS presentation layer in addition to a new "XIVE Exploitation" mode. As a stopgap until we have XIVE exploitation mode, enable XICS emulation mode so that we at least have an interrupt controller. Since the CPPR is local to the current CPU, it cannot be updated for APs when initializing on the BSP. This adds a new function, directly called by the powernv platform code, to initialize the CPPR on AP bringup. Reviewed by: nwhitehorn Differential Revision: https://reviews.freebsd.org/D15492
149 lines
5.0 KiB
C
149 lines
5.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (C) 1995-1997 Wolfgang Solfrank.
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* Copyright (C) 1995-1997 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: cpu.h,v 1.11 2000/05/26 21:19:53 thorpej Exp $
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPU_H_
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#define _MACHINE_CPU_H_
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#include <machine/frame.h>
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#include <machine/pcb.h>
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#include <machine/psl.h>
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/*
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* CPU Feature Attributes
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*
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* These are defined in the PowerPC ELF ABI for the AT_HWCAP vector,
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* and are exported to userland via the machdep.cpu_features
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* sysctl.
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*/
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extern u_long cpu_features;
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extern u_long cpu_features2;
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#define PPC_FEATURE_32 0x80000000 /* Always true */
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#define PPC_FEATURE_64 0x40000000 /* Defined on a 64-bit CPU */
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#define PPC_FEATURE_601_INSTR 0x20000000 /* Defined on a 64-bit CPU */
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#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
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#define PPC_FEATURE_HAS_FPU 0x08000000
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#define PPC_FEATURE_HAS_MMU 0x04000000
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#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
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#define PPC_FEATURE_HAS_SPE 0x00800000
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#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
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#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
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#define PPC_FEATURE_NO_TB 0x00100000
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#define PPC_FEATURE_POWER4 0x00080000
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#define PPC_FEATURE_POWER5 0x00040000
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#define PPC_FEATURE_POWER5_PLUS 0x00020000
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#define PPC_FEATURE_CELL 0x00010000
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#define PPC_FEATURE_BOOKE 0x00008000
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#define PPC_FEATURE_SMT 0x00004000
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#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
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#define PPC_FEATURE_ARCH_2_05 0x00001000
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#define PPC_FEATURE_HAS_DFP 0x00000400
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#define PPC_FEATURE_POWER6_EXT 0x00000200
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#define PPC_FEATURE_ARCH_2_06 0x00000100
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#define PPC_FEATURE_HAS_VSX 0x00000080
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#define PPC_FEATURE_TRUE_LE 0x00000002
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#define PPC_FEATURE_PPC_LE 0x00000001
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#define PPC_FEATURE2_ARCH_2_07 0x80000000
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#define PPC_FEATURE2_HTM 0x40000000
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#define PPC_FEATURE2_DSCR 0x20000000
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#define PPC_FEATURE2_ISEL 0x08000000
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#define PPC_FEATURE2_TAR 0x04000000
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#define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000
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#define PPC_FEATURE2_HTM_NOSC 0x01000000
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#define PPC_FEATURE2_ARCH_3_00 0x00800000
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#define PPC_FEATURE2_HAS_IEEE128 0x00400000
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#define PPC_FEATURE2_DARN 0x00200000
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#define PPC_FEATURE2_SCV 0x00100000
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#define PPC_FEATURE2_HTM_NOSUSPEND 0x01000000
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#define PPC_FEATURE_BITMASK \
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"\20" \
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"\040PPC32\037PPC64\036PPC601\035ALTIVEC\034FPU\033MMU\031UNIFIEDCACHE" \
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"\030SPE\027SPESFP\026DPESFP\025NOTB\024POWER4\023POWER5\022P5PLUS\021CELL"\
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"\020BOOKE\017SMT\016ISNOOP\015ARCH205\013DFP\011ARCH206\010VSX"\
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"\002TRUELE\001PPCLE"
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#define PPC_FEATURE2_BITMASK \
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"\20" \
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"\040ARCH207\037HTM\036DSCR\034ISEL\033TAR\032VCRYPTO\031HTMNOSC" \
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"\030ARCH300\027IEEE128\026DARN\025SCV\024HTMNOSUSP"
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#define TRAPF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
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#define TRAPF_PC(frame) ((frame)->srr0)
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CACHELINE 1
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static __inline u_int64_t
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get_cyclecount(void)
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{
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u_int32_t _upper, _lower;
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u_int64_t _time;
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__asm __volatile(
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"mftb %0\n"
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"mftbu %1"
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: "=r" (_lower), "=r" (_upper));
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_time = (u_int64_t)_upper;
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_time = (_time << 32) + _lower;
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return (_time);
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}
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#define cpu_getstack(td) ((td)->td_frame->fixreg[1])
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#define cpu_spinwait() __asm __volatile("or 27,27,27") /* yield */
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extern char btext[];
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extern char etext[];
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#ifdef __powerpc64__
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extern void enter_idle_powerx(void);
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extern uint64_t can_wakeup;
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extern register_t lpcr;
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#endif
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void cpu_halt(void);
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void cpu_reset(void);
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void cpu_sleep(void);
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void flush_disable_caches(void);
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void fork_trampoline(void);
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void swi_vm(void *);
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#endif /* _MACHINE_CPU_H_ */
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