Support for Pentium events was removed completely in e92a1350b5
.
Don't bump .Dd where we are just removing xrefs.
Reviewed by: emaste
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D31423
806 lines
24 KiB
Groff
806 lines
24 KiB
Groff
.\" Copyright (c) 2008 Joseph Koshy. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd November 12, 2008
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.Dt PMC.CORE 3
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.Os
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.Sh NAME
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.Nm pmc.core
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.Nd measurement events for
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.Tn Intel
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.Tn Core Solo
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and
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.Tn Core Duo
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel
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.Tn "Core Solo"
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and
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.Tn "Core Duo"
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CPUs contain PMCs conforming to version 1 of the
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.Tn Intel
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performance measurement architecture.
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.Pp
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These PMCs are documented in
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.Rs
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.%B IA-32 Intel\(rg Architecture Software Developer's Manual
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.%T Volume 3: System Programming Guide
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.%N Order Number 253669-027US
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.%D July 2008
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.%Q Intel Corporation
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.Re
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.Ss PMC Features
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CPUs conforming to version 1 of the
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.Tn Intel
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performance measurement architecture contain two programmable PMCs of
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class
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.Li PMC_CLASS_IAP .
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The PMCs are 40 bits width and offer the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta Yes
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.It PMC_CAP_INVERT Ta Yes
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta Yes
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta Yes
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.It PMC_CAP_USER Ta Yes
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for these PMCs support the following common
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qualifiers:
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.Bl -tag -width indent
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.It Li cmask= Ns Ar value
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Configure the PMC to increment only if the number of configured
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events measured in a cycle is greater than or equal to
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.Ar value .
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.It Li edge
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Configure the PMC to count the number of de-asserted to asserted
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transitions of the conditions expressed by the other qualifiers.
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If specified, the counter will increment only once whenever a
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condition becomes true, irrespective of the number of clocks during
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which the condition remains true.
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.It Li inv
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Invert the sense of comparison when the
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.Dq Li cmask
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qualifier is present, making the counter increment when the number of
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events per cycle is less than the value specified by the
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.Dq Li cmask
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qualifier.
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.It Li os
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Configure the PMC to count events happening at processor privilege
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level 0.
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.It Li usr
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Configure the PMC to count events occurring at privilege levels 1, 2
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or 3.
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.El
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.Pp
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If neither of the
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.Dq Li os
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or
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.Dq Li usr
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qualifiers are specified, the default is to enable both.
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.Pp
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Events that require core-specificity to be specified use a
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additional qualifier
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.Dq Li core= Ns Ar value ,
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where argument
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.Ar value
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is one of:
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.Bl -tag -width indent -compact
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.It Li all
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Measure event conditions on all cores.
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.It Li this
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Measure event conditions on this core.
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.El
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The default is
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.Dq Li this .
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.Pp
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Events that require an agent qualifier to be specified use an
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additional qualifier
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.Dq Li agent= Ns value ,
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where argument
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.Ar value
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is one of:
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.Bl -tag -width indent -compact
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.It Li this
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Measure events associated with this bus agent.
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.It Li any
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Measure events caused by any bus agent.
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.El
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The default is
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.Dq Li this .
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.Pp
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Events that require a hardware prefetch qualifier to be specified use an
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additional qualifier
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.Dq Li prefetch= Ns Ar value ,
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where argument
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.Ar value
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is one of:
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.Bl -tag -width "exclude" -compact
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.It Li both
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Include all prefetches.
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.It Li only
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Only count hardware prefetches.
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.It Li exclude
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Exclude hardware prefetches.
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.El
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The default is
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.Dq Li both .
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.Pp
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Events that require a cache coherence qualifier to be specified use an
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additional qualifier
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.Dq Li cachestate= Ns Ar value ,
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where argument
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.Ar value
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contains one or more of the following letters:
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.Bl -tag -width indent -compact
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.It Li e
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Count cache lines in the exclusive state.
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.It Li i
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Count cache lines in the invalid state.
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.It Li m
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Count cache lines in the modified state.
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.It Li s
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Count cache lines in the shared state.
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.El
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The default is
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.Dq Li eims .
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.Ss Event Specifiers
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The following event names are case insensitive.
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Whitespace, hyphens and underscore characters in these names are
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ignored.
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.Pp
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Core PMCs support the following events:
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.Bl -tag -width indent
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.It Li BAClears
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.Pq Event E6H , Umask 00H
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The number of BAClear conditions asserted.
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.It Li BTB_Misses
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.Pq Event E2H , Umask 00H
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The number of branches for which the branch table buffer did not
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produce a prediction.
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.It Li Br_BAC_Missp_Exec
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.Pq Event 8AH , Umask 00H
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The number of branch instructions executed that were mispredicted at
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the front end.
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.It Li Br_Bogus
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.Pq Event E4H , Umask 00H
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The number of bogus branches.
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.It Li Br_Call_Exec
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.Pq Event 92H , Umask 00H
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The number of
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.Li CALL
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instructions executed.
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.It Li Br_Call_Missp_Exec
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.Pq Event 93H , Umask 00H
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The number of
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.Li CALL
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instructions executed that were mispredicted.
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.It Li Br_Cnd_Exec
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.Pq Event 8BH , Umask 00H
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The number of conditional branch instructions executed.
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.It Li Br_Cnd_Missp_Exec
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.Pq Event 8CH , Umask 00H
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The number of conditional branch instructions executed that were mispredicted.
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.It Li Br_Ind_Call_Exec
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.Pq Event 94H , Umask 00H
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The number of indirect
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.Li CALL
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instructions executed.
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.It Li Br_Ind_Exec
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.Pq Event 8DH , Umask 00H
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The number of indirect branches executed.
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.It Li Br_Ind_Missp_Exec
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.Pq Event 8EH , Umask 00H
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The number of indirect branch instructions executed that were mispredicted.
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.It Li Br_Inst_Exec
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.Pq Event 88H , Umask 00H
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The number of branch instructions executed including speculative branches.
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.It Li Br_Instr_Decoded
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.Pq Event E0H , Umask 00H
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The number of branch instructions decoded.
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.It Li Br_Instr_Ret
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.Pq Event C4H , Umask 00H
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.Pq Alias Qq "Branch Instruction Retired"
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The number of branch instructions retired.
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This is an architectural performance event.
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.It Li Br_MisPred_Ret
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.Pq Event C5H , Umask 00H
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.Pq Alias Qq "Branch Misses Retired"
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The number of mispredicted branch instructions retired.
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This is an architectural performance event.
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.It Li Br_MisPred_Taken_Ret
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.Pq Event CAH , Umask 00H
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The number of taken and mispredicted branches retired.
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.It Li Br_Missp_Exec
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.Pq Event 89H , Umask 00H
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The number of branch instructions executed and mispredicted at
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execution including branches that were not predicted.
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.It Li Br_Ret_BAC_Missp_Exec
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.Pq Event 91H , Umask 00H
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The number of return branch instructions that were mispredicted at the
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front end.
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.It Li Br_Ret_Exec
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.Pq Event 8FH , Umask 00H
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The number of return branch instructions executed.
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.It Li Br_Ret_Missp_Exec
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.Pq Event 90H , Umask 00H
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The number of return branch instructions executed that were mispredicted.
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.It Li Br_Taken_Ret
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.Pq Event C9H , Umask 00H
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The number of taken branches retired.
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.It Li Bus_BNR_Clocks
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.Pq Event 61H , Umask 00H
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The number of external bus cycles while BNR (bus not ready) was asserted.
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.It Li Bus_DRDY_Clocks Op ,agent= Ns Ar agent
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.Pq Event 62H , Umask 00H
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The number of external bus cycles while DRDY was asserted.
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.It Li Bus_Data_Rcv
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.Pq Event 64H , Umask 40H
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.\" XXX Using the description in Core2 PMC documentation.
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The number of cycles during which the processor is busy receiving data.
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.It Li Bus_Locks_Clocks Op ,core= Ns Ar core
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.Pq Event 63H
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The number of external bus cycles while the bus lock signal was asserted.
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.It Li Bus_Not_In_Use Op ,core= Ns Ar core
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.Pq Event 7DH
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The number of cycles when there is no transaction from the core.
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.It Li Bus_Req_Outstanding Xo
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.Op ,agent= Ns Ar agent
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.Op ,core= Ns Ar core
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.Xc
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.Pq Event 60H
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The weighted cycles of cacheable bus data read requests
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from the data cache unit or hardware prefetcher.
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.It Li Bus_Snoop_Stall
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.Pq Event 7EH , Umask 00H
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The number bus cycles while a bus snoop is stalled.
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.It Li Bus_Snoops Xo
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.Op ,agent= Ns Ar agent
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.Op ,cachestate= Ns Ar mesi
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.Xc
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.Pq Event 77H
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.\" XXX Using the description in Core2 PMC documentation.
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The number of snoop responses to bus transactions.
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.It Li Bus_Trans_Any Op ,agent= Ns Ar agent
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.Pq Event 70H
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The number of completed bus transactions.
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.It Li Bus_Trans_Brd Op ,core= Ns Ar core
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.Pq Event 65H
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The number of read bus transactions.
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.It Li Bus_Trans_Burst Op ,agent= Ns Ar agent
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.Pq Event 6EH
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The number of completed burst transactions.
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Retried transactions may be counted more than once.
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.It Li Bus_Trans_Def Op ,core= Ns Ar core
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.Pq Event 6DH
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The number of completed deferred transactions.
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.It Li Bus_Trans_IO Xo
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.Op ,agent= Ns Ar agent
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.Op ,core= Ns Ar core
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.Xc
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.Pq Event 6CH
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The number of completed I/O transactions counting both reads and
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writes.
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.It Li Bus_Trans_Ifetch Xo
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.Op ,agent= Ns Ar agent
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.Op ,core= Ns Ar core
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.Xc
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.Pq Event 68H
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Completed instruction fetch transactions.
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.It Li Bus_Trans_Inval Xo
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.Op ,agent= Ns Ar agent
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.Op ,core= Ns Ar core
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.Xc
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.Pq Event 69H
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The number completed invalidate transactions.
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.It Li Bus_Trans_Mem Op ,agent= Ns Ar agent
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.Pq Event 6FH
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The number of completed memory transactions.
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.It Li Bus_Trans_P Xo
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.Op ,agent= Ns Ar agent
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.Op ,core= Ns Ar core
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.Xc
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.Pq Event 6BH
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The number of completed partial transactions.
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.It Li Bus_Trans_Pwr Xo
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.Op ,agent= Ns Ar agent
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.Op ,core= Ns Ar core
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.Xc
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.Pq Event 6AH
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The number of completed partial write transactions.
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.It Li Bus_Trans_RFO Xo
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.Op ,agent= Ns Ar agent
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.Op ,core= Ns Ar core
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.Xc
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.Pq Event 66H
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The number of completed read-for-ownership transactions.
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.It Li Bus_Trans_WB Op ,agent= Ns Ar agent
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.Pq Event 67H
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The number of completed write-back transactions from the data cache
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unit, excluding L2 write-backs.
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.It Li Cycles_Div_Busy
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.Pq Event 14H , Umask 00H
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The number of cycles the divider is busy.
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The event is only available on PMC0.
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.It Li Cycles_Int_Masked
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.Pq Event C6H , Umask 00H
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The number of cycles while interrupts were disabled.
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.It Li Cycles_Int_Pending_Masked
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.Pq Event C7H , Umask 00H
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The number of cycles while interrupts were disabled and interrupts
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were pending.
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.It Li DCU_Snoop_To_Share Op ,core= Ns core
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.Pq Event 78H
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The number of data cache unit snoops to L1 cache lines in the shared
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state.
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.It Li DCache_Cache_Lock Op ,cachestate= Ns Ar mesi
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.\" XXX needs clarification
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.Pq Event 42H
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The number of cacheable locked read operations to invalid state.
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.It Li DCache_Cache_LD Op ,cachestate= Ns Ar mesi
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.Pq Event 40H
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The number of cacheable L1 data read operations.
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.It Li DCache_Cache_ST Op ,cachestate= Ns Ar mesi
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.Pq Event 41H
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The number cacheable L1 data write operations.
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.It Li DCache_M_Evict
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.Pq Event 47H , Umask 00H
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The number of M state data cache lines that were evicted.
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.It Li DCache_M_Repl
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.Pq Event 46H , Umask 00H
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The number of M state data cache lines that were allocated.
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.It Li DCache_Pend_Miss
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.Pq Event 48H , Umask 00H
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The weighted cycles an L1 miss was outstanding.
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.It Li DCache_Repl
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.Pq Event 45H , Umask 0FH
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The number of data cache line replacements.
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.It Li Data_Mem_Cache_Ref
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.Pq Event 44H , Umask 02H
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The number of cacheable read and write operations to L1 data cache.
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.It Li Data_Mem_Ref
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.Pq Event 43H , Umask 01H
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The number of L1 data reads and writes, both cacheable and
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un-cacheable.
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.It Li Dbus_Busy Op ,core= Ns Ar core
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.Pq Event 22H
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The number of core cycles during which the data bus was busy.
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.It Li Dbus_Busy_Rd Op ,core= Ns Ar core
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.Pq Event 23H
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The number of cycles during which the data bus was busy transferring
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data to a core.
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.It Li Div
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.Pq Event 13H , Umask 00H
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The number of divide operations including speculative operations for
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integer and floating point divides.
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This event can only be counted on PMC1.
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.It Li Dtlb_Miss
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.Pq Event 49H , Umask 00H
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The number of data references that missed the TLB.
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.It Li ESP_Uops
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.Pq Event D7H , Umask 00H
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The number of ESP folding instructions decoded.
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.It Li EST_Trans Op ,trans= Ns Ar transition
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.Pq Event 3AH
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Count the number of Intel Enhanced SpeedStep transitions.
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The argument
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.Ar transition
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can be one of the following values:
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.Bl -tag -width indent -compact
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.It Li any
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(Umask 00H) Count all transitions.
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.It Li frequency
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(Umask 01H) Count frequency transitions.
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.El
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The default is
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.Dq Li any .
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.It Li FP_Assist
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.Pq Event 11H , Umask 00H
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The number of floating point operations that required microcode
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assists.
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The event is only available on PMC1.
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.It Li FP_Comp_Instr_Ret
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.Pq Event C1H , Umask 00H
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The number of X87 floating point compute instructions retired.
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The event is only available on PMC0.
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.It Li FP_Comps_Op_Exe
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.Pq Event 10H , Umask 00H
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The number of floating point computational instructions executed.
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.It Li FP_MMX_Trans
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.Pq Event CCH , Umask 01H
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The number of transitions from X87 to MMX.
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.It Li Fused_Ld_Uops_Ret
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.Pq Event DAH , Umask 01H
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The number of fused load uops retired.
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.It Li Fused_St_Uops_Ret
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.Pq Event DAH , Umask 02H
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The number of fused store uops retired.
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.It Li Fused_Uops_Ret
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.Pq Event DAH , Umask 00H
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The number of fused uops retired.
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.It Li HW_Int_Rx
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.Pq Event C8H , Umask 00H
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The number of hardware interrupts received.
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.It Li ICache_Misses
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.Pq Event 81H , Umask 00H
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The number of instruction fetch misses in the instruction cache and
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streaming buffers.
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.It Li ICache_Reads
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.Pq Event 80H , Umask 00H
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The number of instruction fetches from the instruction cache and
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streaming buffers counting both cacheable and un-cacheable fetches.
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.It Li IFU_Mem_Stall
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.Pq Event 86H , Umask 00H
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The number of cycles the instruction fetch unit was stalled while
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waiting for data from memory.
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.It Li ILD_Stall
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.Pq Event 87H , Umask 00H
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The number of instruction length decoder stalls.
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.It Li ITLB_Misses
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.Pq Event 85H , Umask 00H
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The number of instruction TLB misses.
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.It Li Instr_Decoded
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.Pq Event D0H , Umask 00H
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The number of instructions decoded.
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.It Li Instr_Ret
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.Pq Event C0H , Umask 00H
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.Pq Alias Qq "Instruction Retired"
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The number of instructions retired.
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This is an architectural performance event.
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.It Li L1_Pref_Req
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.Pq Event 4FH , Umask 00H
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The number of L1 prefetch request due to data cache misses.
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.It Li L2_ADS Op ,core= Ns core
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.Pq Event 21H
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The number of L2 address strobes.
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|
.It Li L2_IFetch Xo
|
|
.Op ,cachestate= Ns Ar mesi
|
|
.Op ,core= Ns Ar core
|
|
.Xc
|
|
.Pq Event 28H
|
|
The number of instruction fetches by the instruction fetch unit from
|
|
L2 cache including speculative fetches.
|
|
.It Li L2_LD Xo
|
|
.Op ,cachestate= Ns Ar mesi
|
|
.Op ,core= Ns Ar core
|
|
.Xc
|
|
.Pq Event 29H
|
|
The number of L2 cache reads.
|
|
.It Li L2_Lines_In Xo
|
|
.Op ,core= Ns Ar core
|
|
.Op ,prefetch= Ns Ar prefetch
|
|
.Xc
|
|
.Pq Event 24H
|
|
The number of L2 cache lines allocated.
|
|
.It Li L2_Lines_Out Xo
|
|
.Op ,core= Ns Ar core
|
|
.Op ,prefetch= Ns Ar prefetch
|
|
.Xc
|
|
.Pq Event 26H
|
|
The number of L2 cache lines evicted.
|
|
.It Li L2_M_Lines_In Op ,core= Ns Ar core
|
|
.Pq Event 25H
|
|
The number of L2 M state cache lines allocated.
|
|
.It Li L2_M_Lines_Out Xo
|
|
.Op ,core= Ns Ar core
|
|
.Op ,prefetch= Ns Ar prefetch
|
|
.Xc
|
|
.Pq Event 27H
|
|
The number of L2 M state cache lines evicted.
|
|
.It Li L2_No_Request_Cycles Xo
|
|
.Op ,cachestate= Ns Ar mesi
|
|
.Op ,core= Ns Ar core
|
|
.Op ,prefetch= Ns Ar prefetch
|
|
.Xc
|
|
.Pq Event 32H
|
|
The number of cycles there was no request to access L2 cache.
|
|
.It Li L2_Reject_Cycles Xo
|
|
.Op ,cachestate= Ns Ar mesi
|
|
.Op ,core= Ns Ar core
|
|
.Op ,prefetch= Ns Ar prefetch
|
|
.Xc
|
|
.Pq Event 30H
|
|
The number of cycles the L2 cache was busy and rejecting new requests.
|
|
.It Li L2_Rqsts Xo
|
|
.Op ,cachestate= Ns Ar mesi
|
|
.Op ,core= Ns Ar core
|
|
.Op ,prefetch= Ns Ar prefetch
|
|
.Xc
|
|
.Pq Event 2EH
|
|
The number of L2 cache requests.
|
|
.It Li L2_ST Xo
|
|
.Op ,cachestate= Ns Ar mesi
|
|
.Op ,core= Ns Ar core
|
|
.Xc
|
|
.Pq Event 2AH
|
|
The number of L2 cache writes including speculative writes.
|
|
.It Li LD_Blocks
|
|
.Pq Event 03H , Umask 00H
|
|
The number of load operations delayed due to store buffer blocks.
|
|
.It Li LLC_Misses
|
|
.Pq Event 2EH , Umask 41H
|
|
The number of cache misses for references to the last level cache,
|
|
excluding misses due to hardware prefetches.
|
|
This is an architectural performance event.
|
|
.It Li LLC_Reference
|
|
The number of references to the last level cache,
|
|
excluding those due to hardware prefetches.
|
|
This is an architectural performance event.
|
|
.Pq Event 2EH , Umask 4FH
|
|
This is an architectural performance event.
|
|
.It Li MMX_Assist
|
|
.Pq Event CDH , Umask 00H
|
|
The number of EMMX instructions executed.
|
|
.It Li MMX_FP_Trans
|
|
.Pq Event CCH , Umask 00H
|
|
The number of transitions from MMX to X87.
|
|
.It Li MMX_Instr_Exec
|
|
.Pq Event B0H , Umask 00H
|
|
The number of MMX instructions executed excluding
|
|
.Li MOVQ
|
|
and
|
|
.Li MOVD
|
|
stores.
|
|
.It Li MMX_Instr_Ret
|
|
.Pq Event CEH , Umask 00H
|
|
The number of MMX instructions retired.
|
|
.It Li Misalign_Mem_Ref
|
|
.Pq Event 05H , Umask 00H
|
|
The number of misaligned data memory references, counting loads and
|
|
stores.
|
|
.It Li Mul
|
|
.Pq Event 12H , Umask 00H
|
|
The number of multiply operations include speculative floating point
|
|
and integer multiplies.
|
|
This event is available on PMC1 only.
|
|
.It Li NonHlt_Ref_Cycles
|
|
.Pq Event 3CH , Umask 01H
|
|
.Pq Alias Qq "Unhalted Reference Cycles"
|
|
The number of non-halted bus cycles.
|
|
This is an architectural performance event.
|
|
.It Li Pref_Rqsts_Dn
|
|
.Pq Event F8H , Umask 00H
|
|
The number of hardware prefetch requests issued in backward streams.
|
|
.It Li Pref_Rqsts_Up
|
|
.Pq Event F0H , Umask 00H
|
|
The number of hardware prefetch requests issued in forward streams.
|
|
.It Li Resource_Stall
|
|
.Pq Event A2H , Umask 00H
|
|
The number of cycles where there is a resource related stall.
|
|
.It Li SD_Drains
|
|
.Pq Event 04H , Umask 00H
|
|
The number of cycles while draining store buffers.
|
|
.It Li SIMD_FP_DP_P_Ret
|
|
.Pq Event D8H , Umask 02H
|
|
The number of SSE/SSE2 packed double precision instructions retired.
|
|
.It Li SIMD_FP_DP_P_Comp_Ret
|
|
.Pq Event D9H , Umask 02H
|
|
The number of SSE/SSE2 packed double precision compute instructions
|
|
retired.
|
|
.It Li SIMD_FP_DP_S_Ret
|
|
.Pq Event D8H , Umask 03H
|
|
The number of SSE/SSE2 scalar double precision instructions retired.
|
|
.It Li SIMD_FP_DP_S_Comp_Ret
|
|
.Pq Event D9H , Umask 03H
|
|
The number of SSE/SSE2 scalar double precision compute instructions
|
|
retired.
|
|
.It Li SIMD_FP_SP_P_Comp_Ret
|
|
.Pq Event D9H , Umask 00H
|
|
The number of SSE/SSE2 packed single precision compute instructions
|
|
retired.
|
|
.It Li SIMD_FP_SP_Ret
|
|
.Pq Event D8H , Umask 00H
|
|
The number of SSE/SSE2 scalar single precision instructions retired,
|
|
both packed and scalar.
|
|
.It Li SIMD_FP_SP_S_Ret
|
|
.Pq Event D8H , Umask 01H
|
|
The number of SSE/SSE2 scalar single precision instructions retired.
|
|
.It Li SIMD_FP_SP_S_Comp_Ret
|
|
.Pq Event D9H , Umask 01H
|
|
The number of SSE/SSE2 single precision compute instructions retired.
|
|
.It Li SIMD_Int_128_Ret
|
|
.Pq Event D8H , Umask 04H
|
|
The number of SSE2 128-bit integer instructions retired.
|
|
.It Li SIMD_Int_Pari_Exec
|
|
.Pq Event B3H , Umask 20H
|
|
The number of SIMD integer packed arithmetic instructions executed.
|
|
.It Li SIMD_Int_Pck_Exec
|
|
.Pq Event B3H , Umask 04H
|
|
The number of SIMD integer pack operations instructions executed.
|
|
.It Li SIMD_Int_Plog_Exec
|
|
.Pq Event B3H , Umask 10H
|
|
The number of SIMD integer packed logical instructions executed.
|
|
.It Li SIMD_Int_Pmul_Exec
|
|
.Pq Event B3H , Umask 01H
|
|
The number of SIMD integer packed multiply instructions executed.
|
|
.It Li SIMD_Int_Psft_Exec
|
|
.Pq Event B3H , Umask 02H
|
|
The number of SIMD integer packed shift instructions executed.
|
|
.It Li SIMD_Int_Sat_Exec
|
|
.Pq Event B1H , Umask 00H
|
|
The number of SIMD integer saturating instructions executed.
|
|
.It Li SIMD_Int_Upck_Exec
|
|
.Pq Event B3H , Umask 08H
|
|
The number of SIMD integer unpack instructions executed.
|
|
.It Li SMC_Detected
|
|
.Pq Event C3H , Umask 00H
|
|
The number of times self-modifying code was detected.
|
|
.It Li SSE_NTStores_Miss
|
|
.Pq Event 4BH , Umask 03H
|
|
The number of times an SSE streaming store instruction missed all caches.
|
|
.It Li SSE_NTStores_Ret
|
|
.Pq Event 07H , Umask 03H
|
|
The number of SSE streaming store instructions executed.
|
|
.It Li SSE_PrefNta_Miss
|
|
.Pq Event 4BH , Umask 00H
|
|
The number of times
|
|
.Li PREFETCHNTA
|
|
missed all caches.
|
|
.It Li SSE_PrefNta_Ret
|
|
.Pq Event 07H , Umask 00H
|
|
The number of
|
|
.Li PREFETCHNTA
|
|
instructions retired.
|
|
.It Li SSE_PrefT1_Miss
|
|
.Pq Event 4BH , Umask 01H
|
|
The number of times
|
|
.Li PREFETCHT1
|
|
missed all caches.
|
|
.It Li SSE_PrefT1_Ret
|
|
.Pq Event 07H , Umask 01H
|
|
The number of
|
|
.Li PREFETCHT1
|
|
instructions retired.
|
|
.It Li SSE_PrefT2_Miss
|
|
.Pq Event 4BH , Umask 02H
|
|
The number of times
|
|
.Li PREFETCHNT2
|
|
missed all caches.
|
|
.It Li SSE_PrefT2_Ret
|
|
.Pq Event 07H , Umask 02H
|
|
The number of
|
|
.Li PREFETCHT2
|
|
instructions retired.
|
|
.It Li Seg_Reg_Loads
|
|
.Pq Event 06H , Umask 00H
|
|
The number of segment register loads.
|
|
.It Li Serial_Execution_Cycles
|
|
.Pq Event 3CH , Umask 02H
|
|
The number of non-halted bus cycles of this code while the other core
|
|
was halted.
|
|
.It Li Thermal_Trip
|
|
.Pq Event 3BH , Umask C0H
|
|
The duration in a thermal trip based on the current core clock.
|
|
.It Li Unfusion
|
|
.Pq Event DBH , Umask 00H
|
|
The number of unfusion events.
|
|
.It Li Unhalted_Core_Cycles
|
|
.Pq Event 3CH , Umask 00H
|
|
The number of core clock cycles when the clock signal on a specific
|
|
core is not halted.
|
|
This is an architectural performance event.
|
|
.It Li Uops_Ret
|
|
.Pq Event C2H , Umask 00H
|
|
The number of micro-ops retired.
|
|
.El
|
|
.Ss Event Name Aliases
|
|
The following table shows the mapping between the PMC-independent
|
|
aliases supported by
|
|
.Lb libpmc
|
|
and the underlying hardware events used.
|
|
.Bl -column "branch-mispredicts" "Description"
|
|
.It Em Alias Ta Em Event
|
|
.It Li branches Ta Li Br_Instr_Ret
|
|
.It Li branch-mispredicts Ta Li Br_MisPred_Ret
|
|
.It Li dc-misses Ta (unsupported)
|
|
.It Li ic-misses Ta Li ICache_Misses
|
|
.It Li instructions Ta Li Instr_Ret
|
|
.It Li interrupts Ta Li HW_Int_Rx
|
|
.It Li unhalted-cycles Ta (unsupported)
|
|
.El
|
|
.Sh PROCESSOR ERRATA
|
|
The following errata affect performance measurement on these
|
|
processors.
|
|
These errata are documented in
|
|
.Rs
|
|
.%B Specification Update
|
|
.%T Intel\(rg CoreTM Duo Processor and Intel\(rg CoreTM Solo Processor on 65 nm Process
|
|
.%N Order Number 309222-017
|
|
.%D July 2008
|
|
.%Q Intel Corporation
|
|
.Re
|
|
.Bl -tag -width indent -compact
|
|
.It AE19
|
|
Data prefetch performance monitoring events can only be enabled
|
|
on a single core.
|
|
.It AE25
|
|
Performance monitoring counters that count external bus events
|
|
may report incorrect values after processor power state transitions.
|
|
.It AE28
|
|
Performance monitoring events for retired floating point operations
|
|
(C1H) may not be accurate.
|
|
.It AE29
|
|
DR3 address match on MOVD/MOVQ/MOVNTQ memory store
|
|
instruction may incorrectly increment performance monitoring count
|
|
for saturating SIMD instructions retired (Event CFH).
|
|
.It AE33
|
|
Hardware prefetch performance monitoring events may be counted
|
|
inaccurately.
|
|
.It AE36
|
|
The
|
|
.Li CPU_CLK_UNHALTED
|
|
performance monitoring event (Event 3CH) counts
|
|
clocks when the processor is in the C1/C2 processor power states.
|
|
.It AE39
|
|
Certain performance monitoring counters related to bus, L2 cache
|
|
and power management are inaccurate.
|
|
.It AE51
|
|
Performance monitoring events for retired instructions (Event C0H) may
|
|
not be accurate.
|
|
.It AE67
|
|
Performance monitoring event
|
|
.Li FP_ASSIST
|
|
may not be accurate.
|
|
.It AE78
|
|
Performance monitoring event for hardware prefetch requests (Event
|
|
4EH) and hardware prefetch request cache misses (Event 4FH) may not be
|
|
accurate.
|
|
.It AE82
|
|
Performance monitoring event
|
|
.Li FP_MMX_TRANS_TO_MMX
|
|
may not count some transitions.
|
|
.El
|
|
.Sh SEE ALSO
|
|
.Xr pmc 3 ,
|
|
.Xr pmc.atom 3 ,
|
|
.Xr pmc.core2 3 ,
|
|
.Xr pmc.iaf 3 ,
|
|
.Xr pmc.k7 3 ,
|
|
.Xr pmc.k8 3 ,
|
|
.Xr pmc.soft 3 ,
|
|
.Xr pmc.tsc 3 ,
|
|
.Xr pmclog 3 ,
|
|
.Xr hwpmc 4
|
|
.Sh HISTORY
|
|
The
|
|
.Nm pmc
|
|
library first appeared in
|
|
.Fx 6.0 .
|
|
.Sh AUTHORS
|
|
The
|
|
.Lb libpmc
|
|
library was written by
|
|
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
|