1212 lines
30 KiB
C
1212 lines
30 KiB
C
/*-
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* Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner A10/A20 and H3 Audio Codec
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/condvar.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/chip.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "sunxi_dma_if.h"
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#include "mixer_if.h"
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struct a10codec_info;
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struct a10codec_config {
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/* mixer class */
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struct kobj_class *mixer_class;
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/* toggle DAC/ADC mute */
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void (*mute)(struct a10codec_info *, int, int);
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/* DRQ types */
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u_int drqtype_codec;
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u_int drqtype_sdram;
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/* register map */
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bus_size_t DPC,
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DAC_FIFOC,
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DAC_FIFOS,
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DAC_TXDATA,
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ADC_FIFOC,
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ADC_FIFOS,
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ADC_RXDATA,
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DAC_CNT,
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ADC_CNT;
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};
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#define TX_TRIG_LEVEL 0xf
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#define RX_TRIG_LEVEL 0x7
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#define DRQ_CLR_CNT 0x3
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#define AC_DAC_DPC(_sc) ((_sc)->cfg->DPC)
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#define DAC_DPC_EN_DA 0x80000000
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#define AC_DAC_FIFOC(_sc) ((_sc)->cfg->DAC_FIFOC)
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#define DAC_FIFOC_FS_SHIFT 29
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#define DAC_FIFOC_FS_MASK (7U << DAC_FIFOC_FS_SHIFT)
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#define DAC_FS_48KHZ 0
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#define DAC_FS_32KHZ 1
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#define DAC_FS_24KHZ 2
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#define DAC_FS_16KHZ 3
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#define DAC_FS_12KHZ 4
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#define DAC_FS_8KHZ 5
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#define DAC_FS_192KHZ 6
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#define DAC_FS_96KHZ 7
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#define DAC_FIFOC_FIFO_MODE_SHIFT 24
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#define DAC_FIFOC_FIFO_MODE_MASK (3U << DAC_FIFOC_FIFO_MODE_SHIFT)
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#define FIFO_MODE_24_31_8 0
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#define FIFO_MODE_16_31_16 0
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#define FIFO_MODE_16_15_0 1
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#define DAC_FIFOC_DRQ_CLR_CNT_SHIFT 21
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#define DAC_FIFOC_DRQ_CLR_CNT_MASK (3U << DAC_FIFOC_DRQ_CLR_CNT_SHIFT)
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#define DAC_FIFOC_TX_TRIG_LEVEL_SHIFT 8
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#define DAC_FIFOC_TX_TRIG_LEVEL_MASK (0x7f << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT)
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#define DAC_FIFOC_MONO_EN (1U << 6)
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#define DAC_FIFOC_TX_BITS (1U << 5)
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#define DAC_FIFOC_DRQ_EN (1U << 4)
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#define DAC_FIFOC_FIFO_FLUSH (1U << 0)
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#define AC_DAC_FIFOS(_sc) ((_sc)->cfg->DAC_FIFOS)
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#define AC_DAC_TXDATA(_sc) ((_sc)->cfg->DAC_TXDATA)
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#define AC_ADC_FIFOC(_sc) ((_sc)->cfg->ADC_FIFOC)
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#define ADC_FIFOC_FS_SHIFT 29
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#define ADC_FIFOC_FS_MASK (7U << ADC_FIFOC_FS_SHIFT)
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#define ADC_FS_48KHZ 0
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#define ADC_FIFOC_EN_AD (1U << 28)
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#define ADC_FIFOC_RX_FIFO_MODE (1U << 24)
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#define ADC_FIFOC_RX_TRIG_LEVEL_SHIFT 8
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#define ADC_FIFOC_RX_TRIG_LEVEL_MASK (0x1f << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT)
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#define ADC_FIFOC_MONO_EN (1U << 7)
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#define ADC_FIFOC_RX_BITS (1U << 6)
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#define ADC_FIFOC_DRQ_EN (1U << 4)
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#define ADC_FIFOC_FIFO_FLUSH (1U << 1)
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#define AC_ADC_FIFOS(_sc) ((_sc)->cfg->ADC_FIFOS)
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#define AC_ADC_RXDATA(_sc) ((_sc)->cfg->ADC_RXDATA)
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#define AC_DAC_CNT(_sc) ((_sc)->cfg->DAC_CNT)
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#define AC_ADC_CNT(_sc) ((_sc)->cfg->ADC_CNT)
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static uint32_t a10codec_fmt[] = {
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SND_FORMAT(AFMT_S16_LE, 1, 0),
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SND_FORMAT(AFMT_S16_LE, 2, 0),
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0
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};
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static struct pcmchan_caps a10codec_pcaps = { 8000, 192000, a10codec_fmt, 0 };
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static struct pcmchan_caps a10codec_rcaps = { 8000, 48000, a10codec_fmt, 0 };
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struct a10codec_info;
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struct a10codec_chinfo {
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struct snd_dbuf *buffer;
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struct pcm_channel *channel;
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struct a10codec_info *parent;
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bus_dmamap_t dmamap;
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void *dmaaddr;
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bus_addr_t physaddr;
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bus_size_t fifo;
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device_t dmac;
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void *dmachan;
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int dir;
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int run;
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uint32_t pos;
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uint32_t format;
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uint32_t blocksize;
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uint32_t speed;
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};
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struct a10codec_info {
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device_t dev;
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struct resource *res[2];
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struct mtx *lock;
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bus_dma_tag_t dmat;
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unsigned dmasize;
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void *ih;
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struct a10codec_config *cfg;
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struct a10codec_chinfo play;
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struct a10codec_chinfo rec;
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};
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static struct resource_spec a10codec_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define CODEC_ANALOG_READ(sc, reg) bus_read_4((sc)->res[1], (reg))
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#define CODEC_ANALOG_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val))
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#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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/*
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* A10/A20 mixer interface
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*/
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#define A10_DAC_ACTL 0x10
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#define A10_DACAREN (1U << 31)
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#define A10_DACALEN (1U << 30)
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#define A10_MIXEN (1U << 29)
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#define A10_DACPAS (1U << 8)
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#define A10_PAMUTE (1U << 6)
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#define A10_PAVOL_SHIFT 0
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#define A10_PAVOL_MASK (0x3f << A10_PAVOL_SHIFT)
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#define A10_ADC_ACTL 0x28
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#define A10_ADCREN (1U << 31)
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#define A10_ADCLEN (1U << 30)
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#define A10_PREG1EN (1U << 29)
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#define A10_PREG2EN (1U << 28)
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#define A10_VMICEN (1U << 27)
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#define A10_ADCG_SHIFT 20
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#define A10_ADCG_MASK (7U << A10_ADCG_SHIFT)
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#define A10_ADCIS_SHIFT 17
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#define A10_ADCIS_MASK (7U << A10_ADCIS_SHIFT)
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#define A10_ADC_IS_LINEIN 0
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#define A10_ADC_IS_FMIN 1
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#define A10_ADC_IS_MIC1 2
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#define A10_ADC_IS_MIC2 3
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#define A10_ADC_IS_MIC1_L_MIC2_R 4
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#define A10_ADC_IS_MIC1_LR_MIC2_LR 5
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#define A10_ADC_IS_OMIX 6
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#define A10_ADC_IS_LINEIN_L_MIC1_R 7
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#define A10_LNRDF (1U << 16)
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#define A10_LNPREG_SHIFT 13
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#define A10_LNPREG_MASK (7U << A10_LNPREG_SHIFT)
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#define A10_PA_EN (1U << 4)
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#define A10_DDE (1U << 3)
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static int
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a10_mixer_init(struct snd_mixer *m)
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{
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struct a10codec_info *sc = mix_getdevinfo(m);
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uint32_t val;
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mix_setdevs(m, SOUND_MASK_VOLUME | SOUND_MASK_LINE | SOUND_MASK_RECLEV);
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mix_setrecdevs(m, SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC);
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/* Unmute input source to PA */
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val = CODEC_READ(sc, A10_DAC_ACTL);
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val |= A10_PAMUTE;
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CODEC_WRITE(sc, A10_DAC_ACTL, val);
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/* Enable PA */
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val = CODEC_READ(sc, A10_ADC_ACTL);
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val |= A10_PA_EN;
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CODEC_WRITE(sc, A10_ADC_ACTL, val);
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return (0);
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}
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static const struct a10_mixer {
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unsigned reg;
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unsigned mask;
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unsigned shift;
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} a10_mixers[SOUND_MIXER_NRDEVICES] = {
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[SOUND_MIXER_VOLUME] = { A10_DAC_ACTL, A10_PAVOL_MASK,
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A10_PAVOL_SHIFT },
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[SOUND_MIXER_LINE] = { A10_ADC_ACTL, A10_LNPREG_MASK,
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A10_LNPREG_SHIFT },
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[SOUND_MIXER_RECLEV] = { A10_ADC_ACTL, A10_ADCG_MASK,
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A10_ADCG_SHIFT },
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};
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static int
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a10_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left,
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unsigned right)
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{
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struct a10codec_info *sc = mix_getdevinfo(m);
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uint32_t val;
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unsigned nvol, max;
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max = a10_mixers[dev].mask >> a10_mixers[dev].shift;
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nvol = (left * max) / 100;
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val = CODEC_READ(sc, a10_mixers[dev].reg);
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val &= ~a10_mixers[dev].mask;
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val |= (nvol << a10_mixers[dev].shift);
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CODEC_WRITE(sc, a10_mixers[dev].reg, val);
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left = right = (left * 100) / max;
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return (left | (right << 8));
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}
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static uint32_t
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a10_mixer_setrecsrc(struct snd_mixer *m, uint32_t src)
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{
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struct a10codec_info *sc = mix_getdevinfo(m);
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uint32_t val;
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val = CODEC_READ(sc, A10_ADC_ACTL);
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switch (src) {
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case SOUND_MASK_LINE: /* line-in */
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val &= ~A10_ADCIS_MASK;
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val |= (A10_ADC_IS_LINEIN << A10_ADCIS_SHIFT);
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break;
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case SOUND_MASK_MIC: /* MIC1 */
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val &= ~A10_ADCIS_MASK;
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val |= (A10_ADC_IS_MIC1 << A10_ADCIS_SHIFT);
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break;
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case SOUND_MASK_LINE1: /* MIC2 */
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val &= ~A10_ADCIS_MASK;
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val |= (A10_ADC_IS_MIC2 << A10_ADCIS_SHIFT);
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break;
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default:
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break;
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}
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CODEC_WRITE(sc, A10_ADC_ACTL, val);
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switch ((val & A10_ADCIS_MASK) >> A10_ADCIS_SHIFT) {
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case A10_ADC_IS_LINEIN:
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return (SOUND_MASK_LINE);
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case A10_ADC_IS_MIC1:
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return (SOUND_MASK_MIC);
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case A10_ADC_IS_MIC2:
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return (SOUND_MASK_LINE1);
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default:
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return (0);
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}
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}
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static void
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a10_mute(struct a10codec_info *sc, int mute, int dir)
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{
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uint32_t val;
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if (dir == PCMDIR_PLAY) {
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val = CODEC_READ(sc, A10_DAC_ACTL);
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if (mute) {
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/* Disable DAC analog l/r channels and output mixer */
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val &= ~A10_DACAREN;
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val &= ~A10_DACALEN;
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val &= ~A10_DACPAS;
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} else {
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/* Enable DAC analog l/r channels and output mixer */
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val |= A10_DACAREN;
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val |= A10_DACALEN;
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val |= A10_DACPAS;
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}
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CODEC_WRITE(sc, A10_DAC_ACTL, val);
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} else {
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val = CODEC_READ(sc, A10_ADC_ACTL);
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if (mute) {
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/* Disable ADC analog l/r channels, MIC1 preamp,
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* and VMIC pin voltage
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*/
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val &= ~A10_ADCREN;
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val &= ~A10_ADCLEN;
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val &= ~A10_PREG1EN;
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val &= ~A10_VMICEN;
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} else {
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/* Enable ADC analog l/r channels, MIC1 preamp,
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* and VMIC pin voltage
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*/
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val |= A10_ADCREN;
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val |= A10_ADCLEN;
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val |= A10_PREG1EN;
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val |= A10_VMICEN;
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}
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CODEC_WRITE(sc, A10_ADC_ACTL, val);
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}
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}
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static kobj_method_t a10_mixer_methods[] = {
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KOBJMETHOD(mixer_init, a10_mixer_init),
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KOBJMETHOD(mixer_set, a10_mixer_set),
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KOBJMETHOD(mixer_setrecsrc, a10_mixer_setrecsrc),
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KOBJMETHOD_END
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};
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MIXER_DECLARE(a10_mixer);
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/*
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* H3 mixer interface
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*/
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#define H3_PR_CFG 0x00
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#define H3_AC_PR_RST (1 << 28)
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#define H3_AC_PR_RW (1 << 24)
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#define H3_AC_PR_ADDR_SHIFT 16
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#define H3_AC_PR_ADDR_MASK (0x1f << H3_AC_PR_ADDR_SHIFT)
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#define H3_ACDA_PR_WDAT_SHIFT 8
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#define H3_ACDA_PR_WDAT_MASK (0xff << H3_ACDA_PR_WDAT_SHIFT)
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#define H3_ACDA_PR_RDAT_SHIFT 0
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#define H3_ACDA_PR_RDAT_MASK (0xff << H3_ACDA_PR_RDAT_SHIFT)
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#define H3_LOMIXSC 0x01
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#define H3_LOMIXSC_LDAC (1 << 1)
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#define H3_ROMIXSC 0x02
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#define H3_ROMIXSC_RDAC (1 << 1)
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#define H3_DAC_PA_SRC 0x03
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#define H3_DACAREN (1 << 7)
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#define H3_DACALEN (1 << 6)
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#define H3_RMIXEN (1 << 5)
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#define H3_LMIXEN (1 << 4)
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#define H3_LINEIN_GCTR 0x05
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#define H3_LINEING_SHIFT 4
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#define H3_LINEING_MASK (0x7 << H3_LINEING_SHIFT)
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#define H3_MIC_GCTR 0x06
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#define H3_MIC1_GAIN_SHIFT 4
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#define H3_MIC1_GAIN_MASK (0x7 << H3_MIC1_GAIN_SHIFT)
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#define H3_MIC2_GAIN_SHIFT 0
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#define H3_MIC2_GAIN_MASK (0x7 << H3_MIC2_GAIN_SHIFT)
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#define H3_PAEN_CTR 0x07
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#define H3_LINEOUTEN (1 << 7)
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#define H3_LINEOUT_VOLC 0x09
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#define H3_LINEOUTVOL_SHIFT 3
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#define H3_LINEOUTVOL_MASK (0x1f << H3_LINEOUTVOL_SHIFT)
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#define H3_MIC2G_LINEOUT_CTR 0x0a
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#define H3_LINEOUT_LSEL (1 << 3)
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#define H3_LINEOUT_RSEL (1 << 2)
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#define H3_LADCMIXSC 0x0c
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#define H3_RADCMIXSC 0x0d
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#define H3_ADCMIXSC_MIC1 (1 << 6)
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#define H3_ADCMIXSC_MIC2 (1 << 5)
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#define H3_ADCMIXSC_LINEIN (1 << 2)
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#define H3_ADCMIXSC_OMIXER (3 << 0)
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#define H3_ADC_AP_EN 0x0f
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#define H3_ADCREN (1 << 7)
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#define H3_ADCLEN (1 << 6)
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#define H3_ADCG_SHIFT 0
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#define H3_ADCG_MASK (0x7 << H3_ADCG_SHIFT)
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static u_int
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h3_pr_read(struct a10codec_info *sc, u_int addr)
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{
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uint32_t val;
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/* Read current value */
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val = CODEC_ANALOG_READ(sc, H3_PR_CFG);
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/* De-assert reset */
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val |= H3_AC_PR_RST;
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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/* Read mode */
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val &= ~H3_AC_PR_RW;
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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/* Set address */
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val &= ~H3_AC_PR_ADDR_MASK;
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val |= (addr << H3_AC_PR_ADDR_SHIFT);
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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/* Read data */
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return (CODEC_ANALOG_READ(sc , H3_PR_CFG) & H3_ACDA_PR_RDAT_MASK);
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}
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static void
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h3_pr_write(struct a10codec_info *sc, u_int addr, u_int data)
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{
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uint32_t val;
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/* Read current value */
|
|
val = CODEC_ANALOG_READ(sc, H3_PR_CFG);
|
|
|
|
/* De-assert reset */
|
|
val |= H3_AC_PR_RST;
|
|
CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
|
|
|
|
/* Set address */
|
|
val &= ~H3_AC_PR_ADDR_MASK;
|
|
val |= (addr << H3_AC_PR_ADDR_SHIFT);
|
|
CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
|
|
|
|
/* Write data */
|
|
val &= ~H3_ACDA_PR_WDAT_MASK;
|
|
val |= (data << H3_ACDA_PR_WDAT_SHIFT);
|
|
CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
|
|
|
|
/* Write mode */
|
|
val |= H3_AC_PR_RW;
|
|
CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
|
|
}
|
|
|
|
static void
|
|
h3_pr_set_clear(struct a10codec_info *sc, u_int addr, u_int set, u_int clr)
|
|
{
|
|
u_int old, new;
|
|
|
|
old = h3_pr_read(sc, addr);
|
|
new = set | (old & ~clr);
|
|
h3_pr_write(sc, addr, new);
|
|
}
|
|
|
|
static int
|
|
h3_mixer_init(struct snd_mixer *m)
|
|
{
|
|
int rid=1;
|
|
pcell_t reg[2];
|
|
phandle_t analogref;
|
|
struct a10codec_info *sc = mix_getdevinfo(m);
|
|
|
|
if (OF_getencprop(ofw_bus_get_node(sc->dev), "allwinner,codec-analog-controls",
|
|
&analogref, sizeof(analogref)) <= 0) {
|
|
return (ENXIO);
|
|
}
|
|
|
|
if (OF_getencprop(OF_node_from_xref(analogref), "reg",
|
|
reg, sizeof(reg)) <= 0) {
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->res[1] = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, &rid, reg[0],
|
|
reg[0]+reg[1], reg[1], RF_ACTIVE );
|
|
|
|
if (sc->res[1] == NULL) {
|
|
return (ENXIO);
|
|
}
|
|
|
|
mix_setdevs(m, SOUND_MASK_PCM | SOUND_MASK_VOLUME | SOUND_MASK_RECLEV |
|
|
SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1);
|
|
mix_setrecdevs(m, SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1 |
|
|
SOUND_MASK_IMIX);
|
|
|
|
pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
|
|
|
|
/* Right & Left LINEOUT enable */
|
|
h3_pr_set_clear(sc, H3_PAEN_CTR, H3_LINEOUTEN, 0);
|
|
h3_pr_set_clear(sc, H3_MIC2G_LINEOUT_CTR,
|
|
H3_LINEOUT_LSEL | H3_LINEOUT_RSEL, 0);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static const struct h3_mixer {
|
|
unsigned reg;
|
|
unsigned mask;
|
|
unsigned shift;
|
|
} h3_mixers[SOUND_MIXER_NRDEVICES] = {
|
|
[SOUND_MIXER_VOLUME] = { H3_LINEOUT_VOLC, H3_LINEOUTVOL_MASK,
|
|
H3_LINEOUTVOL_SHIFT },
|
|
[SOUND_MIXER_RECLEV] = { H3_ADC_AP_EN, H3_ADCG_MASK,
|
|
H3_ADCG_SHIFT },
|
|
[SOUND_MIXER_LINE] = { H3_LINEIN_GCTR, H3_LINEING_MASK,
|
|
H3_LINEING_SHIFT },
|
|
[SOUND_MIXER_MIC] = { H3_MIC_GCTR, H3_MIC1_GAIN_MASK,
|
|
H3_MIC1_GAIN_SHIFT },
|
|
[SOUND_MIXER_LINE1] = { H3_MIC_GCTR, H3_MIC2_GAIN_MASK,
|
|
H3_MIC2_GAIN_SHIFT },
|
|
};
|
|
|
|
static int
|
|
h3_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left,
|
|
unsigned right)
|
|
{
|
|
struct a10codec_info *sc = mix_getdevinfo(m);
|
|
unsigned nvol, max;
|
|
|
|
max = h3_mixers[dev].mask >> h3_mixers[dev].shift;
|
|
nvol = (left * max) / 100;
|
|
|
|
h3_pr_set_clear(sc, h3_mixers[dev].reg,
|
|
nvol << h3_mixers[dev].shift, h3_mixers[dev].mask);
|
|
|
|
left = right = (left * 100) / max;
|
|
return (left | (right << 8));
|
|
}
|
|
|
|
static uint32_t
|
|
h3_mixer_setrecsrc(struct snd_mixer *m, uint32_t src)
|
|
{
|
|
struct a10codec_info *sc = mix_getdevinfo(m);
|
|
uint32_t val;
|
|
|
|
val = 0;
|
|
src &= (SOUND_MASK_LINE | SOUND_MASK_MIC |
|
|
SOUND_MASK_LINE1 | SOUND_MASK_IMIX);
|
|
|
|
if ((src & SOUND_MASK_LINE) != 0) /* line-in */
|
|
val |= H3_ADCMIXSC_LINEIN;
|
|
if ((src & SOUND_MASK_MIC) != 0) /* MIC1 */
|
|
val |= H3_ADCMIXSC_MIC1;
|
|
if ((src & SOUND_MASK_LINE1) != 0) /* MIC2 */
|
|
val |= H3_ADCMIXSC_MIC2;
|
|
if ((src & SOUND_MASK_IMIX) != 0) /* l/r output mixer */
|
|
val |= H3_ADCMIXSC_OMIXER;
|
|
|
|
h3_pr_write(sc, H3_LADCMIXSC, val);
|
|
h3_pr_write(sc, H3_RADCMIXSC, val);
|
|
|
|
return (src);
|
|
}
|
|
|
|
static void
|
|
h3_mute(struct a10codec_info *sc, int mute, int dir)
|
|
{
|
|
if (dir == PCMDIR_PLAY) {
|
|
if (mute) {
|
|
/* Mute DAC l/r channels to output mixer */
|
|
h3_pr_set_clear(sc, H3_LOMIXSC, 0, H3_LOMIXSC_LDAC);
|
|
h3_pr_set_clear(sc, H3_ROMIXSC, 0, H3_ROMIXSC_RDAC);
|
|
/* Disable DAC analog l/r channels and output mixer */
|
|
h3_pr_set_clear(sc, H3_DAC_PA_SRC,
|
|
0, H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN);
|
|
} else {
|
|
/* Enable DAC analog l/r channels and output mixer */
|
|
h3_pr_set_clear(sc, H3_DAC_PA_SRC,
|
|
H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN, 0);
|
|
/* Unmute DAC l/r channels to output mixer */
|
|
h3_pr_set_clear(sc, H3_LOMIXSC, H3_LOMIXSC_LDAC, 0);
|
|
h3_pr_set_clear(sc, H3_ROMIXSC, H3_ROMIXSC_RDAC, 0);
|
|
}
|
|
} else {
|
|
if (mute) {
|
|
/* Disable ADC analog l/r channels */
|
|
h3_pr_set_clear(sc, H3_ADC_AP_EN,
|
|
0, H3_ADCREN | H3_ADCLEN);
|
|
} else {
|
|
/* Enable ADC analog l/r channels */
|
|
h3_pr_set_clear(sc, H3_ADC_AP_EN,
|
|
H3_ADCREN | H3_ADCLEN, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
static kobj_method_t h3_mixer_methods[] = {
|
|
KOBJMETHOD(mixer_init, h3_mixer_init),
|
|
KOBJMETHOD(mixer_set, h3_mixer_set),
|
|
KOBJMETHOD(mixer_setrecsrc, h3_mixer_setrecsrc),
|
|
KOBJMETHOD_END
|
|
};
|
|
MIXER_DECLARE(h3_mixer);
|
|
|
|
/*
|
|
* Channel interface
|
|
*/
|
|
|
|
static void
|
|
a10codec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
|
|
{
|
|
struct a10codec_chinfo *ch = arg;
|
|
|
|
if (error != 0)
|
|
return;
|
|
|
|
ch->physaddr = segs[0].ds_addr;
|
|
}
|
|
|
|
static void
|
|
a10codec_transfer(struct a10codec_chinfo *ch)
|
|
{
|
|
bus_addr_t src, dst;
|
|
int error;
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
src = ch->physaddr + ch->pos;
|
|
dst = ch->fifo;
|
|
} else {
|
|
src = ch->fifo;
|
|
dst = ch->physaddr + ch->pos;
|
|
}
|
|
|
|
error = SUNXI_DMA_TRANSFER(ch->dmac, ch->dmachan, src, dst,
|
|
ch->blocksize);
|
|
if (error) {
|
|
ch->run = 0;
|
|
device_printf(ch->parent->dev, "DMA transfer failed: %d\n",
|
|
error);
|
|
}
|
|
}
|
|
|
|
static void
|
|
a10codec_dmaconfig(struct a10codec_chinfo *ch)
|
|
{
|
|
struct a10codec_info *sc = ch->parent;
|
|
struct sunxi_dma_config conf;
|
|
|
|
memset(&conf, 0, sizeof(conf));
|
|
conf.src_width = conf.dst_width = 16;
|
|
conf.src_burst_len = conf.dst_burst_len = 4;
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
conf.dst_noincr = true;
|
|
conf.src_drqtype = sc->cfg->drqtype_sdram;
|
|
conf.dst_drqtype = sc->cfg->drqtype_codec;
|
|
} else {
|
|
conf.src_noincr = true;
|
|
conf.src_drqtype = sc->cfg->drqtype_codec;
|
|
conf.dst_drqtype = sc->cfg->drqtype_sdram;
|
|
}
|
|
|
|
SUNXI_DMA_SET_CONFIG(ch->dmac, ch->dmachan, &conf);
|
|
}
|
|
|
|
static void
|
|
a10codec_dmaintr(void *priv)
|
|
{
|
|
struct a10codec_chinfo *ch = priv;
|
|
unsigned bufsize;
|
|
|
|
bufsize = sndbuf_getsize(ch->buffer);
|
|
|
|
ch->pos += ch->blocksize;
|
|
if (ch->pos >= bufsize)
|
|
ch->pos -= bufsize;
|
|
|
|
if (ch->run) {
|
|
chn_intr(ch->channel);
|
|
a10codec_transfer(ch);
|
|
}
|
|
}
|
|
|
|
static unsigned
|
|
a10codec_fs(struct a10codec_chinfo *ch)
|
|
{
|
|
switch (ch->speed) {
|
|
case 48000:
|
|
return (DAC_FS_48KHZ);
|
|
case 24000:
|
|
return (DAC_FS_24KHZ);
|
|
case 12000:
|
|
return (DAC_FS_12KHZ);
|
|
case 192000:
|
|
return (DAC_FS_192KHZ);
|
|
case 32000:
|
|
return (DAC_FS_32KHZ);
|
|
case 16000:
|
|
return (DAC_FS_16KHZ);
|
|
case 8000:
|
|
return (DAC_FS_8KHZ);
|
|
case 96000:
|
|
return (DAC_FS_96KHZ);
|
|
default:
|
|
return (DAC_FS_48KHZ);
|
|
}
|
|
}
|
|
|
|
static void
|
|
a10codec_start(struct a10codec_chinfo *ch)
|
|
{
|
|
struct a10codec_info *sc = ch->parent;
|
|
uint32_t val;
|
|
|
|
ch->pos = 0;
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
/* Flush DAC FIFO */
|
|
CODEC_WRITE(sc, AC_DAC_FIFOC(sc), DAC_FIFOC_FIFO_FLUSH);
|
|
|
|
/* Clear DAC FIFO status */
|
|
CODEC_WRITE(sc, AC_DAC_FIFOS(sc),
|
|
CODEC_READ(sc, AC_DAC_FIFOS(sc)));
|
|
|
|
/* Unmute output */
|
|
sc->cfg->mute(sc, 0, ch->dir);
|
|
|
|
/* Configure DAC DMA channel */
|
|
a10codec_dmaconfig(ch);
|
|
|
|
/* Configure DAC FIFO */
|
|
CODEC_WRITE(sc, AC_DAC_FIFOC(sc),
|
|
(AFMT_CHANNEL(ch->format) == 1 ? DAC_FIFOC_MONO_EN : 0) |
|
|
(a10codec_fs(ch) << DAC_FIFOC_FS_SHIFT) |
|
|
(FIFO_MODE_16_15_0 << DAC_FIFOC_FIFO_MODE_SHIFT) |
|
|
(DRQ_CLR_CNT << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) |
|
|
(TX_TRIG_LEVEL << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT));
|
|
|
|
/* Enable DAC DRQ */
|
|
val = CODEC_READ(sc, AC_DAC_FIFOC(sc));
|
|
val |= DAC_FIFOC_DRQ_EN;
|
|
CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val);
|
|
} else {
|
|
/* Flush ADC FIFO */
|
|
CODEC_WRITE(sc, AC_ADC_FIFOC(sc), ADC_FIFOC_FIFO_FLUSH);
|
|
|
|
/* Clear ADC FIFO status */
|
|
CODEC_WRITE(sc, AC_ADC_FIFOS(sc),
|
|
CODEC_READ(sc, AC_ADC_FIFOS(sc)));
|
|
|
|
/* Unmute input */
|
|
sc->cfg->mute(sc, 0, ch->dir);
|
|
|
|
/* Configure ADC DMA channel */
|
|
a10codec_dmaconfig(ch);
|
|
|
|
/* Configure ADC FIFO */
|
|
CODEC_WRITE(sc, AC_ADC_FIFOC(sc),
|
|
ADC_FIFOC_EN_AD |
|
|
ADC_FIFOC_RX_FIFO_MODE |
|
|
(AFMT_CHANNEL(ch->format) == 1 ? ADC_FIFOC_MONO_EN : 0) |
|
|
(a10codec_fs(ch) << ADC_FIFOC_FS_SHIFT) |
|
|
(RX_TRIG_LEVEL << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT));
|
|
|
|
/* Enable ADC DRQ */
|
|
val = CODEC_READ(sc, AC_ADC_FIFOC(sc));
|
|
val |= ADC_FIFOC_DRQ_EN;
|
|
CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val);
|
|
}
|
|
|
|
/* Start DMA transfer */
|
|
a10codec_transfer(ch);
|
|
}
|
|
|
|
static void
|
|
a10codec_stop(struct a10codec_chinfo *ch)
|
|
{
|
|
struct a10codec_info *sc = ch->parent;
|
|
|
|
/* Disable DMA channel */
|
|
SUNXI_DMA_HALT(ch->dmac, ch->dmachan);
|
|
|
|
sc->cfg->mute(sc, 1, ch->dir);
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
/* Disable DAC DRQ */
|
|
CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 0);
|
|
} else {
|
|
/* Disable ADC DRQ */
|
|
CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 0);
|
|
}
|
|
}
|
|
|
|
static void *
|
|
a10codec_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
|
|
struct pcm_channel *c, int dir)
|
|
{
|
|
struct a10codec_info *sc = devinfo;
|
|
struct a10codec_chinfo *ch = dir == PCMDIR_PLAY ? &sc->play : &sc->rec;
|
|
phandle_t xref;
|
|
pcell_t *cells;
|
|
int ncells, error;
|
|
|
|
error = ofw_bus_parse_xref_list_alloc(ofw_bus_get_node(sc->dev),
|
|
"dmas", "#dma-cells", dir == PCMDIR_PLAY ? 1 : 0,
|
|
&xref, &ncells, &cells);
|
|
if (error != 0) {
|
|
device_printf(sc->dev, "cannot parse 'dmas' property\n");
|
|
return (NULL);
|
|
}
|
|
OF_prop_free(cells);
|
|
|
|
ch->parent = sc;
|
|
ch->channel = c;
|
|
ch->buffer = b;
|
|
ch->dir = dir;
|
|
ch->fifo = rman_get_start(sc->res[0]) +
|
|
(dir == PCMDIR_REC ? AC_ADC_RXDATA(sc) : AC_DAC_TXDATA(sc));
|
|
|
|
ch->dmac = OF_device_from_xref(xref);
|
|
if (ch->dmac == NULL) {
|
|
device_printf(sc->dev, "cannot find DMA controller\n");
|
|
device_printf(sc->dev, "xref = 0x%x\n", (u_int)xref);
|
|
return (NULL);
|
|
}
|
|
ch->dmachan = SUNXI_DMA_ALLOC(ch->dmac, false, a10codec_dmaintr, ch);
|
|
if (ch->dmachan == NULL) {
|
|
device_printf(sc->dev, "cannot allocate DMA channel\n");
|
|
return (NULL);
|
|
}
|
|
|
|
error = bus_dmamem_alloc(sc->dmat, &ch->dmaaddr,
|
|
BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &ch->dmamap);
|
|
if (error != 0) {
|
|
device_printf(sc->dev, "cannot allocate channel buffer\n");
|
|
return (NULL);
|
|
}
|
|
error = bus_dmamap_load(sc->dmat, ch->dmamap, ch->dmaaddr,
|
|
sc->dmasize, a10codec_dmamap_cb, ch, BUS_DMA_NOWAIT);
|
|
if (error != 0) {
|
|
device_printf(sc->dev, "cannot load DMA map\n");
|
|
return (NULL);
|
|
}
|
|
memset(ch->dmaaddr, 0, sc->dmasize);
|
|
|
|
if (sndbuf_setup(ch->buffer, ch->dmaaddr, sc->dmasize) != 0) {
|
|
device_printf(sc->dev, "cannot setup sndbuf\n");
|
|
return (NULL);
|
|
}
|
|
|
|
return (ch);
|
|
}
|
|
|
|
static int
|
|
a10codec_chan_free(kobj_t obj, void *data)
|
|
{
|
|
struct a10codec_chinfo *ch = data;
|
|
struct a10codec_info *sc = ch->parent;
|
|
|
|
SUNXI_DMA_FREE(ch->dmac, ch->dmachan);
|
|
bus_dmamap_unload(sc->dmat, ch->dmamap);
|
|
bus_dmamem_free(sc->dmat, ch->dmaaddr, ch->dmamap);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
a10codec_chan_setformat(kobj_t obj, void *data, uint32_t format)
|
|
{
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
ch->format = format;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static uint32_t
|
|
a10codec_chan_setspeed(kobj_t obj, void *data, uint32_t speed)
|
|
{
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
/*
|
|
* The codec supports full duplex operation but both DAC and ADC
|
|
* use the same source clock (PLL2). Limit the available speeds to
|
|
* those supported by a 24576000 Hz input.
|
|
*/
|
|
switch (speed) {
|
|
case 8000:
|
|
case 12000:
|
|
case 16000:
|
|
case 24000:
|
|
case 32000:
|
|
case 48000:
|
|
ch->speed = speed;
|
|
break;
|
|
case 96000:
|
|
case 192000:
|
|
/* 96 KHz / 192 KHz mode only supported for playback */
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
ch->speed = speed;
|
|
} else {
|
|
ch->speed = 48000;
|
|
}
|
|
break;
|
|
case 44100:
|
|
ch->speed = 48000;
|
|
break;
|
|
case 22050:
|
|
ch->speed = 24000;
|
|
break;
|
|
case 11025:
|
|
ch->speed = 12000;
|
|
break;
|
|
default:
|
|
ch->speed = 48000;
|
|
break;
|
|
}
|
|
|
|
return (ch->speed);
|
|
}
|
|
|
|
static uint32_t
|
|
a10codec_chan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
|
|
{
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
ch->blocksize = blocksize & ~3;
|
|
|
|
return (ch->blocksize);
|
|
}
|
|
|
|
static int
|
|
a10codec_chan_trigger(kobj_t obj, void *data, int go)
|
|
{
|
|
struct a10codec_chinfo *ch = data;
|
|
struct a10codec_info *sc = ch->parent;
|
|
|
|
if (!PCMTRIG_COMMON(go))
|
|
return (0);
|
|
|
|
snd_mtxlock(sc->lock);
|
|
switch (go) {
|
|
case PCMTRIG_START:
|
|
ch->run = 1;
|
|
a10codec_stop(ch);
|
|
a10codec_start(ch);
|
|
break;
|
|
case PCMTRIG_STOP:
|
|
case PCMTRIG_ABORT:
|
|
ch->run = 0;
|
|
a10codec_stop(ch);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
snd_mtxunlock(sc->lock);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static uint32_t
|
|
a10codec_chan_getptr(kobj_t obj, void *data)
|
|
{
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
return (ch->pos);
|
|
}
|
|
|
|
static struct pcmchan_caps *
|
|
a10codec_chan_getcaps(kobj_t obj, void *data)
|
|
{
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
return (&a10codec_pcaps);
|
|
} else {
|
|
return (&a10codec_rcaps);
|
|
}
|
|
}
|
|
|
|
static kobj_method_t a10codec_chan_methods[] = {
|
|
KOBJMETHOD(channel_init, a10codec_chan_init),
|
|
KOBJMETHOD(channel_free, a10codec_chan_free),
|
|
KOBJMETHOD(channel_setformat, a10codec_chan_setformat),
|
|
KOBJMETHOD(channel_setspeed, a10codec_chan_setspeed),
|
|
KOBJMETHOD(channel_setblocksize, a10codec_chan_setblocksize),
|
|
KOBJMETHOD(channel_trigger, a10codec_chan_trigger),
|
|
KOBJMETHOD(channel_getptr, a10codec_chan_getptr),
|
|
KOBJMETHOD(channel_getcaps, a10codec_chan_getcaps),
|
|
KOBJMETHOD_END
|
|
};
|
|
CHANNEL_DECLARE(a10codec_chan);
|
|
|
|
/*
|
|
* Device interface
|
|
*/
|
|
|
|
static const struct a10codec_config a10_config = {
|
|
.mixer_class = &a10_mixer_class,
|
|
.mute = a10_mute,
|
|
.drqtype_codec = 19,
|
|
.drqtype_sdram = 22,
|
|
.DPC = 0x00,
|
|
.DAC_FIFOC = 0x04,
|
|
.DAC_FIFOS = 0x08,
|
|
.DAC_TXDATA = 0x0c,
|
|
.ADC_FIFOC = 0x1c,
|
|
.ADC_FIFOS = 0x20,
|
|
.ADC_RXDATA = 0x24,
|
|
.DAC_CNT = 0x30,
|
|
.ADC_CNT = 0x34,
|
|
};
|
|
|
|
static const struct a10codec_config h3_config = {
|
|
.mixer_class = &h3_mixer_class,
|
|
.mute = h3_mute,
|
|
.drqtype_codec = 15,
|
|
.drqtype_sdram = 1,
|
|
.DPC = 0x00,
|
|
.DAC_FIFOC = 0x04,
|
|
.DAC_FIFOS = 0x08,
|
|
.DAC_TXDATA = 0x20,
|
|
.ADC_FIFOC = 0x10,
|
|
.ADC_FIFOS = 0x14,
|
|
.ADC_RXDATA = 0x18,
|
|
.DAC_CNT = 0x40,
|
|
.ADC_CNT = 0x44,
|
|
};
|
|
|
|
static struct ofw_compat_data compat_data[] = {
|
|
{ "allwinner,sun4i-a10-codec", (uintptr_t)&a10_config },
|
|
{ "allwinner,sun7i-a20-codec", (uintptr_t)&a10_config },
|
|
{ "allwinner,sun8i-h3-codec", (uintptr_t)&h3_config },
|
|
{ NULL, 0 }
|
|
};
|
|
|
|
static int
|
|
a10codec_probe(device_t dev)
|
|
{
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Allwinner Audio Codec");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
a10codec_attach(device_t dev)
|
|
{
|
|
struct a10codec_info *sc;
|
|
char status[SND_STATUSLEN];
|
|
struct gpiobus_pin *pa_pin;
|
|
phandle_t node;
|
|
clk_t clk_bus, clk_codec;
|
|
hwreset_t rst;
|
|
uint32_t val;
|
|
int error;
|
|
|
|
node = ofw_bus_get_node(dev);
|
|
|
|
sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
|
|
sc->cfg = (void *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
|
|
sc->dev = dev;
|
|
sc->lock = snd_mtxcreate(device_get_nameunit(dev), "a10codec softc");
|
|
|
|
if (bus_alloc_resources(dev, a10codec_spec, sc->res)) {
|
|
device_printf(dev, "cannot allocate resources for device\n");
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
sc->dmasize = 131072;
|
|
error = bus_dma_tag_create(
|
|
bus_get_dma_tag(dev),
|
|
4, sc->dmasize, /* alignment, boundary */
|
|
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
NULL, NULL, /* filter, filterarg */
|
|
sc->dmasize, 1, /* maxsize, nsegs */
|
|
sc->dmasize, 0, /* maxsegsize, flags */
|
|
NULL, NULL, /* lockfunc, lockarg */
|
|
&sc->dmat);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot create DMA tag\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Get clocks */
|
|
if (clk_get_by_ofw_name(dev, 0, "apb", &clk_bus) != 0 &&
|
|
clk_get_by_ofw_name(dev, 0, "ahb", &clk_bus) != 0) {
|
|
device_printf(dev, "cannot find bus clock\n");
|
|
goto fail;
|
|
}
|
|
if (clk_get_by_ofw_name(dev, 0, "codec", &clk_codec) != 0) {
|
|
device_printf(dev, "cannot find codec clock\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Gating bus clock for codec */
|
|
if (clk_enable(clk_bus) != 0) {
|
|
device_printf(dev, "cannot enable bus clock\n");
|
|
goto fail;
|
|
}
|
|
/* Activate audio codec clock. According to the A10 and A20 user
|
|
* manuals, Audio_pll can be either 24.576MHz or 22.5792MHz. Most
|
|
* audio sampling rates require an 24.576MHz input clock with the
|
|
* exception of 44.1kHz, 22.05kHz, and 11.025kHz. Unfortunately,
|
|
* both capture and playback use the same clock source so to
|
|
* safely support independent full duplex operation, we use a fixed
|
|
* 24.576MHz clock source and don't advertise native support for
|
|
* the three sampling rates that require a 22.5792MHz input.
|
|
*/
|
|
error = clk_set_freq(clk_codec, 24576000, CLK_SET_ROUND_DOWN);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot set codec clock frequency\n");
|
|
goto fail;
|
|
}
|
|
/* Enable audio codec clock */
|
|
error = clk_enable(clk_codec);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot enable codec clock\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* De-assert hwreset */
|
|
if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
|
|
error = hwreset_deassert(rst);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot de-assert reset\n");
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
/* Enable DAC */
|
|
val = CODEC_READ(sc, AC_DAC_DPC(sc));
|
|
val |= DAC_DPC_EN_DA;
|
|
CODEC_WRITE(sc, AC_DAC_DPC(sc), val);
|
|
|
|
if (mixer_init(dev, sc->cfg->mixer_class, sc)) {
|
|
device_printf(dev, "mixer_init failed\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Unmute PA */
|
|
if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios",
|
|
&pa_pin) == 0) {
|
|
error = gpio_pin_set_active(pa_pin, 1);
|
|
if (error != 0)
|
|
device_printf(dev, "failed to unmute PA\n");
|
|
}
|
|
|
|
pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
|
|
|
|
if (pcm_register(dev, sc, 1, 1)) {
|
|
device_printf(dev, "pcm_register failed\n");
|
|
goto fail;
|
|
}
|
|
|
|
pcm_addchan(dev, PCMDIR_PLAY, &a10codec_chan_class, sc);
|
|
pcm_addchan(dev, PCMDIR_REC, &a10codec_chan_class, sc);
|
|
|
|
snprintf(status, SND_STATUSLEN, "at %s", ofw_bus_get_name(dev));
|
|
pcm_setstatus(dev, status);
|
|
|
|
return (0);
|
|
|
|
fail:
|
|
bus_release_resources(dev, a10codec_spec, sc->res);
|
|
snd_mtxfree(sc->lock);
|
|
free(sc, M_DEVBUF);
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static device_method_t a10codec_pcm_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, a10codec_probe),
|
|
DEVMETHOD(device_attach, a10codec_attach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t a10codec_pcm_driver = {
|
|
"pcm",
|
|
a10codec_pcm_methods,
|
|
PCM_SOFTC_SIZE,
|
|
};
|
|
|
|
DRIVER_MODULE(a10codec, simplebus, a10codec_pcm_driver, 0, 0);
|
|
MODULE_DEPEND(a10codec, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
|
|
MODULE_VERSION(a10codec, 1);
|