342 lines
8.1 KiB
C
342 lines
8.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/gpio.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "gpio_if.h"
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#include "syscon_if.h"
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struct a37x0_gpio_softc {
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device_t sc_busdev;
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int sc_type;
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uint32_t sc_max_pins;
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uint32_t sc_npins;
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struct syscon *syscon;
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};
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/* Memory regions. */
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#define A37X0_GPIO 0
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#define A37X0_INTR 1
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/* North Bridge / South Bridge. */
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#define A37X0_NB_GPIO 1
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#define A37X0_SB_GPIO 2
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#define A37X0_GPIO_WRITE(_sc, _off, _val) \
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SYSCON_WRITE_4((_sc)->syscon, (_off), (_val))
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#define A37X0_GPIO_READ(_sc, _off) \
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SYSCON_READ_4((_sc)->syscon, (_off))
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#define A37X0_GPIO_BIT(_p) (1U << ((_p) % 32))
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#define A37X0_GPIO_OUT_EN(_p) (0x0 + ((_p) / 32) * 4)
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#define A37X0_GPIO_LATCH(_p) (0x8 + ((_p) / 32) * 4)
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#define A37X0_GPIO_INPUT(_p) (0x10 + ((_p) / 32) * 4)
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#define A37X0_GPIO_OUTPUT(_p) (0x18 + ((_p) / 32) * 4)
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#define A37X0_GPIO_SEL 0x30
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static struct ofw_compat_data compat_data[] = {
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{ "marvell,armada3710-nb-pinctrl", A37X0_NB_GPIO },
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{ "marvell,armada3710-sb-pinctrl", A37X0_SB_GPIO },
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{ NULL, 0 }
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};
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static phandle_t
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a37x0_gpio_get_node(device_t bus, device_t dev)
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{
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return (ofw_bus_get_node(bus));
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}
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static device_t
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a37x0_gpio_get_bus(device_t dev)
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{
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struct a37x0_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->sc_busdev);
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}
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static int
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a37x0_gpio_pin_max(device_t dev, int *maxpin)
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{
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struct a37x0_gpio_softc *sc;
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sc = device_get_softc(dev);
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*maxpin = sc->sc_npins - 1;
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return (0);
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}
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static int
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a37x0_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct a37x0_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->sc_npins)
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return (EINVAL);
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snprintf(name, GPIOMAXNAME, "pin %d", pin);
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return (0);
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}
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static int
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a37x0_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct a37x0_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->sc_npins)
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return (EINVAL);
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*caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
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return (0);
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}
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static int
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a37x0_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct a37x0_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (pin >= sc->sc_npins)
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return (EINVAL);
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reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
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if ((reg & A37X0_GPIO_BIT(pin)) != 0)
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*flags = GPIO_PIN_OUTPUT;
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else
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*flags = GPIO_PIN_INPUT;
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return (0);
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}
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static int
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a37x0_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct a37x0_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (pin >= sc->sc_npins)
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return (EINVAL);
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reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
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if (flags & GPIO_PIN_OUTPUT)
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reg |= A37X0_GPIO_BIT(pin);
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else
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reg &= ~A37X0_GPIO_BIT(pin);
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A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUT_EN(pin), reg);
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return (0);
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}
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static int
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a37x0_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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{
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struct a37x0_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (pin >= sc->sc_npins)
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return (EINVAL);
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reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
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if ((reg & A37X0_GPIO_BIT(pin)) != 0)
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reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
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else
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reg = A37X0_GPIO_READ(sc, A37X0_GPIO_INPUT(pin));
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*val = ((reg & A37X0_GPIO_BIT(pin)) != 0) ? 1 : 0;
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return (0);
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}
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static int
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a37x0_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val)
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{
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struct a37x0_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (pin >= sc->sc_npins)
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return (EINVAL);
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reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
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if (val != 0)
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reg |= A37X0_GPIO_BIT(pin);
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else
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reg &= ~A37X0_GPIO_BIT(pin);
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A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);
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return (0);
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}
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static int
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a37x0_gpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct a37x0_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (pin >= sc->sc_npins)
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return (EINVAL);
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reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
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if ((reg & A37X0_GPIO_BIT(pin)) == 0)
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return (EINVAL);
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reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
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reg ^= A37X0_GPIO_BIT(pin);
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A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);
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return (0);
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}
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static int
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a37x0_gpio_probe(device_t dev)
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{
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const char *desc;
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struct a37x0_gpio_softc *sc;
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if (!OF_hasprop(ofw_bus_get_node(dev), "gpio-controller"))
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return (ENXIO);
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sc = device_get_softc(dev);
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sc->sc_type = ofw_bus_search_compatible(
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device_get_parent(dev), compat_data)->ocd_data;
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switch (sc->sc_type) {
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case A37X0_NB_GPIO:
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sc->sc_max_pins = 36;
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desc = "Armada 37x0 North Bridge GPIO Controller";
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break;
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case A37X0_SB_GPIO:
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sc->sc_max_pins = 30;
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desc = "Armada 37x0 South Bridge GPIO Controller";
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break;
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default:
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return (ENXIO);
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}
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device_set_desc(dev, desc);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a37x0_gpio_attach(device_t dev)
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{
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int err, ncells;
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pcell_t *ranges;
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struct a37x0_gpio_softc *sc;
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sc = device_get_softc(dev);
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err = syscon_get_handle_default(dev, &sc->syscon);
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if (err != 0) {
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device_printf(dev, "Cannot get syscon handle from parent\n");
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return (ENXIO);
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}
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/* Read and verify the "gpio-ranges" property. */
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ncells = OF_getencprop_alloc(ofw_bus_get_node(dev), "gpio-ranges",
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(void **)&ranges);
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if (ncells == -1)
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return (ENXIO);
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if (ncells != sizeof(*ranges) * 4 || ranges[1] != 0 || ranges[2] != 0) {
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OF_prop_free(ranges);
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return (ENXIO);
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}
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sc->sc_npins = ranges[3];
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OF_prop_free(ranges);
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/* Check the number of pins in the DTS vs HW capabilities. */
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if (sc->sc_npins > sc->sc_max_pins)
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return (ENXIO);
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sc->sc_busdev = gpiobus_attach_bus(dev);
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if (sc->sc_busdev == NULL)
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return (ENXIO);
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return (0);
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}
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static int
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a37x0_gpio_detach(device_t dev)
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{
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return (EBUSY);
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}
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static device_method_t a37x0_gpio_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, a37x0_gpio_probe),
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DEVMETHOD(device_attach, a37x0_gpio_attach),
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DEVMETHOD(device_detach, a37x0_gpio_detach),
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/* GPIO interface */
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DEVMETHOD(gpio_get_bus, a37x0_gpio_get_bus),
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DEVMETHOD(gpio_pin_max, a37x0_gpio_pin_max),
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DEVMETHOD(gpio_pin_getname, a37x0_gpio_pin_getname),
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DEVMETHOD(gpio_pin_getcaps, a37x0_gpio_pin_getcaps),
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DEVMETHOD(gpio_pin_getflags, a37x0_gpio_pin_getflags),
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DEVMETHOD(gpio_pin_setflags, a37x0_gpio_pin_setflags),
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DEVMETHOD(gpio_pin_get, a37x0_gpio_pin_get),
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DEVMETHOD(gpio_pin_set, a37x0_gpio_pin_set),
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DEVMETHOD(gpio_pin_toggle, a37x0_gpio_pin_toggle),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_node, a37x0_gpio_get_node),
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DEVMETHOD_END
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};
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static driver_t a37x0_gpio_driver = {
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"gpio",
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a37x0_gpio_methods,
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sizeof(struct a37x0_gpio_softc),
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};
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EARLY_DRIVER_MODULE(a37x0_gpio, simple_mfd, a37x0_gpio_driver, 0, 0,
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BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);
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