45c98dac39
Import from vendor-sys/ena-com/1.1.4.1 SVN rev.: 317516 Version: 1.1.4.1 Obtained from: Amazon.com, Inc.
138 lines
5.6 KiB
C
138 lines
5.6 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ENA_REGS_H_
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#define _ENA_REGS_H_
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/* ena_registers offsets */
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#define ENA_REGS_VERSION_OFF 0x0
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#define ENA_REGS_CONTROLLER_VERSION_OFF 0x4
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#define ENA_REGS_CAPS_OFF 0x8
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#define ENA_REGS_CAPS_EXT_OFF 0xc
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#define ENA_REGS_AQ_BASE_LO_OFF 0x10
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#define ENA_REGS_AQ_BASE_HI_OFF 0x14
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#define ENA_REGS_AQ_CAPS_OFF 0x18
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#define ENA_REGS_ACQ_BASE_LO_OFF 0x20
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#define ENA_REGS_ACQ_BASE_HI_OFF 0x24
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#define ENA_REGS_ACQ_CAPS_OFF 0x28
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#define ENA_REGS_AQ_DB_OFF 0x2c
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#define ENA_REGS_ACQ_TAIL_OFF 0x30
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#define ENA_REGS_AENQ_CAPS_OFF 0x34
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#define ENA_REGS_AENQ_BASE_LO_OFF 0x38
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#define ENA_REGS_AENQ_BASE_HI_OFF 0x3c
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#define ENA_REGS_AENQ_HEAD_DB_OFF 0x40
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#define ENA_REGS_AENQ_TAIL_OFF 0x44
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#define ENA_REGS_INTR_MASK_OFF 0x4c
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#define ENA_REGS_DEV_CTL_OFF 0x54
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#define ENA_REGS_DEV_STS_OFF 0x58
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#define ENA_REGS_MMIO_REG_READ_OFF 0x5c
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#define ENA_REGS_MMIO_RESP_LO_OFF 0x60
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#define ENA_REGS_MMIO_RESP_HI_OFF 0x64
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#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68
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/* version register */
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#define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff
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#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8
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#define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00
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/* controller_version register */
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#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff
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#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8
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#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00
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#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16
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#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000
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#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24
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#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000
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/* caps register */
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#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1
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#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1
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#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e
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#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8
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#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00
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#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16
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#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000
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/* aq_caps register */
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#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff
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#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16
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#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000
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/* acq_caps register */
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#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff
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#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16
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#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000
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/* aenq_caps register */
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#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff
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#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16
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#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000
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/* dev_ctl register */
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#define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1
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#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1
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#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2
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#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 2
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#define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4
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#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3
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#define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8
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/* dev_sts register */
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#define ENA_REGS_DEV_STS_READY_MASK 0x1
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#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1
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#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2
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#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2
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#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4
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#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3
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#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8
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#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4
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#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10
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#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5
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#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20
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#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6
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#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40
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#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7
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#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80
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/* mmio_reg_read register */
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#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff
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#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16
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#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000
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/* rss_ind_entry_update register */
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#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff
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#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16
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#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000
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#endif /*_ENA_REGS_H_ */
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