According to the Intel manual https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3b-part-2-manual.pdf the Thermal Status (0) and Thermal Status Log (1) bits report only a high temperature on the CPU, not a critical temperature as suggested in the coretemp driver. Check the Critical Temperature Log (5) instead. The critical temperature waives guarantees of correct function, therefore the CPU could have for example written some wrong values into memory at that point and the OS should be stopped ASAP as the state is no longer reliable. Reviewed by: imp (confirmed descriptions of bits, linux ignores these bits) Pull Request: https://github.com/freebsd/freebsd-src/pull/562
444 lines
12 KiB
C
444 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Device driver for Intel's On Die thermal sensor via MSR.
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* First introduced in Intel's Core line of processors.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/proc.h> /* for curthread */
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#include <sys/smp.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <machine/specialreg.h>
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#include <machine/cpufunc.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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#define TZ_ZEROC 2731
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#define THERM_CRITICAL_STATUS_LOG 0x20
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#define THERM_CRITICAL_STATUS 0x10
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#define THERM_STATUS_LOG 0x02
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#define THERM_STATUS 0x01
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#define THERM_STATUS_TEMP_SHIFT 16
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#define THERM_STATUS_TEMP_MASK 0x7f
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#define THERM_STATUS_RES_SHIFT 27
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#define THERM_STATUS_RES_MASK 0x0f
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#define THERM_STATUS_VALID_SHIFT 31
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#define THERM_STATUS_VALID_MASK 0x01
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struct coretemp_softc {
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device_t sc_dev;
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int sc_tjmax;
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unsigned int sc_throttle_log;
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};
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/*
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* Device methods.
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*/
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static void coretemp_identify(driver_t *driver, device_t parent);
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static int coretemp_probe(device_t dev);
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static int coretemp_attach(device_t dev);
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static int coretemp_detach(device_t dev);
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static uint64_t coretemp_get_thermal_msr(int cpu);
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static void coretemp_clear_thermal_msr(int cpu);
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static int coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS);
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static int coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS);
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static device_method_t coretemp_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, coretemp_identify),
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DEVMETHOD(device_probe, coretemp_probe),
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DEVMETHOD(device_attach, coretemp_attach),
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DEVMETHOD(device_detach, coretemp_detach),
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DEVMETHOD_END
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};
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static driver_t coretemp_driver = {
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"coretemp",
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coretemp_methods,
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sizeof(struct coretemp_softc),
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};
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enum therm_info {
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CORETEMP_TEMP,
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CORETEMP_DELTA,
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CORETEMP_RESOLUTION,
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CORETEMP_TJMAX,
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};
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DRIVER_MODULE(coretemp, cpu, coretemp_driver, NULL, NULL);
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static void
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coretemp_identify(driver_t *driver, device_t parent)
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{
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device_t child;
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u_int regs[4];
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/* Make sure we're not being doubly invoked. */
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if (device_find_child(parent, "coretemp", -1) != NULL)
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return;
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/* Check that CPUID 0x06 is supported and the vendor is Intel.*/
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if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL)
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return;
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/*
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* CPUID 0x06 returns 1 if the processor has on-die thermal
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* sensors. EBX[0:3] contains the number of sensors.
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*/
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do_cpuid(0x06, regs);
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if ((regs[0] & 0x1) != 1)
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return;
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/*
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* We add a child for each CPU since settings must be performed
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* on each CPU in the SMP case.
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*/
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child = device_add_child(parent, "coretemp", device_get_unit(parent));
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if (child == NULL)
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device_printf(parent, "add coretemp child failed\n");
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}
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static int
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coretemp_probe(device_t dev)
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{
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if (resource_disabled("coretemp", 0))
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return (ENXIO);
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device_set_desc(dev, "CPU On-Die Thermal Sensors");
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if (!bootverbose && device_get_unit(dev) != 0)
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device_quiet(dev);
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return (BUS_PROBE_GENERIC);
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}
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static int
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coretemp_attach(device_t dev)
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{
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struct coretemp_softc *sc = device_get_softc(dev);
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device_t pdev;
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uint64_t msr;
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int cpu_model, cpu_stepping;
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int ret, tjtarget;
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struct sysctl_oid *oid;
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struct sysctl_ctx_list *ctx;
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sc->sc_dev = dev;
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pdev = device_get_parent(dev);
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cpu_model = CPUID_TO_MODEL(cpu_id);
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cpu_stepping = CPUID_TO_STEPPING(cpu_id);
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/*
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* Some CPUs, namely the PIII, don't have thermal sensors, but
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* report them when the CPUID check is performed in
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* coretemp_identify(). This leads to a later GPF when the sensor
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* is queried via a MSR, so we stop here.
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*/
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if (cpu_model < 0xe)
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return (ENXIO);
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#if 0 /*
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* XXXrpaulo: I have this CPU model and when it returns from C3
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* coretemp continues to function properly.
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*/
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/*
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* Check for errata AE18.
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* "Processor Digital Thermal Sensor (DTS) Readout stops
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* updating upon returning from C3/C4 state."
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*
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* Adapted from the Linux coretemp driver.
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*/
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if (cpu_model == 0xe && cpu_stepping < 0xc) {
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msr = rdmsr(MSR_BIOS_SIGN);
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msr = msr >> 32;
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if (msr < 0x39) {
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device_printf(dev, "not supported (Intel errata "
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"AE18), try updating your BIOS\n");
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return (ENXIO);
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}
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}
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#endif
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/*
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* Use 100C as the initial value.
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*/
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sc->sc_tjmax = 100;
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if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
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/*
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* On some Core 2 CPUs, there's an undocumented MSR that
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* can tell us if Tj(max) is 100 or 85.
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*
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* The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted
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* from the Linux coretemp driver.
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*/
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msr = rdmsr(MSR_IA32_EXT_CONFIG);
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if (msr & (1 << 30))
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sc->sc_tjmax = 85;
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} else if (cpu_model == 0x17) {
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switch (cpu_stepping) {
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case 0x6: /* Mobile Core 2 Duo */
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sc->sc_tjmax = 105;
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break;
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default: /* Unknown stepping */
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break;
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}
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} else if (cpu_model == 0x1c) {
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switch (cpu_stepping) {
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case 0xa: /* 45nm Atom D400, N400 and D500 series */
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sc->sc_tjmax = 100;
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break;
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default:
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sc->sc_tjmax = 90;
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break;
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}
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} else {
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/*
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* Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
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*
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* This method is described in Intel white paper "CPU
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* Monitoring With DTS/PECI". (#322683)
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*/
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ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
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if (ret == 0) {
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tjtarget = (msr >> 16) & 0xff;
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/*
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* On earlier generation of processors, the value
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* obtained from IA32_TEMPERATURE_TARGET register is
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* an offset that needs to be summed with a model
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* specific base. It is however not clear what
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* these numbers are, with the publicly available
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* documents from Intel.
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*
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* For now, we consider [70, 110]C range, as
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* described in #322683, as "reasonable" and accept
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* these values whenever the MSR is available for
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* read, regardless the CPU model.
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*/
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if (tjtarget >= 70 && tjtarget <= 110)
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sc->sc_tjmax = tjtarget;
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else
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device_printf(dev, "Tj(target) value %d "
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"does not seem right.\n", tjtarget);
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} else
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device_printf(dev, "Can not get Tj(target) "
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"from your CPU, using 100C.\n");
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}
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if (bootverbose)
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device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
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ctx = device_get_sysctl_ctx(dev);
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oid = SYSCTL_ADD_NODE(ctx,
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SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)), OID_AUTO,
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"coretemp", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
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"Per-CPU thermal information");
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/*
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* Add the MIBs to dev.cpu.N and dev.cpu.N.coretemp.
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*/
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SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)),
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OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
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dev, CORETEMP_TEMP, coretemp_get_val_sysctl, "IK",
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"Current temperature");
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SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "delta",
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CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_DELTA,
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coretemp_get_val_sysctl, "I",
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"Delta between TCC activation and current temperature");
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SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "resolution",
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CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_RESOLUTION,
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coretemp_get_val_sysctl, "I",
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"Resolution of CPU thermal sensor");
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SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "tjmax",
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CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_TJMAX,
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coretemp_get_val_sysctl, "IK",
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"TCC activation temperature");
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SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
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"throttle_log", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0,
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coretemp_throttle_log_sysctl, "I",
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"Set to 1 if the thermal sensor has tripped");
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return (0);
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}
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static int
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coretemp_detach(device_t dev)
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{
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return (0);
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}
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struct coretemp_args {
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u_int msr;
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uint64_t val;
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};
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/*
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* The digital temperature reading is located at bit 16
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* of MSR_THERM_STATUS.
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*
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* There is a bit on that MSR that indicates whether the
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* temperature is valid or not.
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*
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* The temperature is computed by subtracting the temperature
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* reading by Tj(max).
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*/
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static uint64_t
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coretemp_get_thermal_msr(int cpu)
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{
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uint64_t res;
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x86_msr_op(MSR_THERM_STATUS, MSR_OP_RENDEZVOUS_ONE | MSR_OP_READ |
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MSR_OP_CPUID(cpu), 0, &res);
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return (res);
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}
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static void
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coretemp_clear_thermal_msr(int cpu)
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{
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x86_msr_op(MSR_THERM_STATUS, MSR_OP_RENDEZVOUS_ONE | MSR_OP_WRITE |
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MSR_OP_CPUID(cpu), 0, NULL);
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}
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static int
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coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS)
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{
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device_t dev;
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uint64_t msr;
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int val, tmp;
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struct coretemp_softc *sc;
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enum therm_info type;
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char stemp[16];
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dev = (device_t) arg1;
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msr = coretemp_get_thermal_msr(device_get_unit(dev));
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sc = device_get_softc(dev);
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type = arg2;
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if (((msr >> THERM_STATUS_VALID_SHIFT) & THERM_STATUS_VALID_MASK) != 1) {
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val = -1;
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} else {
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switch (type) {
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case CORETEMP_TEMP:
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tmp = (msr >> THERM_STATUS_TEMP_SHIFT) &
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THERM_STATUS_TEMP_MASK;
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val = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC;
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break;
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case CORETEMP_DELTA:
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val = (msr >> THERM_STATUS_TEMP_SHIFT) &
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THERM_STATUS_TEMP_MASK;
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break;
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case CORETEMP_RESOLUTION:
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val = (msr >> THERM_STATUS_RES_SHIFT) &
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THERM_STATUS_RES_MASK;
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break;
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case CORETEMP_TJMAX:
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val = sc->sc_tjmax * 10 + TZ_ZEROC;
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break;
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}
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}
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if (msr & THERM_STATUS_LOG) {
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coretemp_clear_thermal_msr(device_get_unit(dev));
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sc->sc_throttle_log = 1;
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/*
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* Check for Critical Temperature Status and Critical
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* Temperature Log. It doesn't really matter if the
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* current temperature is invalid because the "Critical
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* Temperature Log" bit will tell us if the Critical
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* Temperature has * been reached in past. It's not
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* directly related to the current temperature.
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*
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* If we reach a critical level, allow devctl(4)
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* to catch this and shutdown the system.
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*/
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if (msr & THERM_CRITICAL_STATUS) {
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tmp = (msr >> THERM_STATUS_TEMP_SHIFT) &
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THERM_STATUS_TEMP_MASK;
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tmp = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC;
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device_printf(dev, "critical temperature detected, "
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"suggest system shutdown\n");
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snprintf(stemp, sizeof(stemp), "%d", tmp);
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devctl_notify("coretemp", "Thermal", stemp,
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"notify=0xcc");
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}
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}
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return (sysctl_handle_int(oidp, &val, 0, req));
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}
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static int
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coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS)
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{
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device_t dev;
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uint64_t msr;
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int error, val;
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struct coretemp_softc *sc;
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dev = (device_t) arg1;
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msr = coretemp_get_thermal_msr(device_get_unit(dev));
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sc = device_get_softc(dev);
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if (msr & THERM_STATUS_LOG) {
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coretemp_clear_thermal_msr(device_get_unit(dev));
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sc->sc_throttle_log = 1;
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}
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val = sc->sc_throttle_log;
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error = sysctl_handle_int(oidp, &val, 0, req);
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if (error || !req->newptr)
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return (error);
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else if (val != 0)
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return (EINVAL);
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coretemp_clear_thermal_msr(device_get_unit(dev));
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sc->sc_throttle_log = 0;
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return (0);
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}
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