718bdb6a71
Approved by: bz (mentor) Reviewed by: bz (mentor), mhorne Differential Revision: https://reviews.freebsd.org/D39946 MFC after: 3 weeks
603 lines
18 KiB
C
603 lines
18 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright © 2021-2022 Dmitry Salychev
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* Copyright © 2022 Mathew McBride
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DPAA2_NI_H
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#define _DPAA2_NI_H
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#include <sys/rman.h>
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#include <sys/bus.h>
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#include <sys/queue.h>
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#include <sys/taskqueue.h>
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#include <sys/mbuf.h>
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#include <sys/param.h>
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#include <sys/socket.h>
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#include <sys/buf_ring.h>
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#include <sys/proc.h>
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#include <sys/mutex.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include "dpaa2_types.h"
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#include "dpaa2_mcp.h"
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#include "dpaa2_swp.h"
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#include "dpaa2_io.h"
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#include "dpaa2_mac.h"
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#include "dpaa2_ni_dpkg.h"
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/* Name of the DPAA2 network interface. */
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#define DPAA2_NI_IFNAME "dpni"
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/* Maximum resources per DPNI: 16 DPIOs + 16 DPCONs + 1 DPBP + 1 DPMCP. */
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#define DPAA2_NI_MAX_RESOURCES 34
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#define DPAA2_NI_MSI_COUNT 1 /* MSIs per DPNI */
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#define DPAA2_NI_MAX_CHANNELS 16 /* to distribute ingress traffic to cores */
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#define DPAA2_NI_MAX_TCS 8 /* traffic classes per DPNI */
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#define DPAA2_NI_MAX_POOLS 8 /* buffer pools per DPNI */
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/* Maximum number of Rx buffers. */
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#define DPAA2_NI_BUFS_INIT (50u * DPAA2_SWP_BUFS_PER_CMD)
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#define DPAA2_NI_BUFS_MAX (1 << 15) /* 15 bits for buffer index max. */
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/* Maximum number of buffers allocated per Tx ring. */
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#define DPAA2_NI_BUFS_PER_TX (1 << 7)
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#define DPAA2_NI_MAX_BPTX (1 << 8) /* 8 bits for buffer index max. */
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/* Number of the DPNI statistics counters. */
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#define DPAA2_NI_STAT_COUNTERS 7u
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#define DPAA2_NI_STAT_SYSCTLS 9u
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/* Error and status bits in the frame annotation status word. */
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#define DPAA2_NI_FAS_DISC 0x80000000 /* debug frame */
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#define DPAA2_NI_FAS_MS 0x40000000 /* MACSEC frame */
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#define DPAA2_NI_FAS_PTP 0x08000000
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#define DPAA2_NI_FAS_MC 0x04000000 /* Ethernet multicast frame */
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#define DPAA2_NI_FAS_BC 0x02000000 /* Ethernet broadcast frame */
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#define DPAA2_NI_FAS_KSE 0x00040000
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#define DPAA2_NI_FAS_EOFHE 0x00020000
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#define DPAA2_NI_FAS_MNLE 0x00010000
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#define DPAA2_NI_FAS_TIDE 0x00008000
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#define DPAA2_NI_FAS_PIEE 0x00004000
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#define DPAA2_NI_FAS_FLE 0x00002000 /* Frame length error */
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#define DPAA2_NI_FAS_FPE 0x00001000 /* Frame physical error */
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#define DPAA2_NI_FAS_PTE 0x00000080
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#define DPAA2_NI_FAS_ISP 0x00000040
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#define DPAA2_NI_FAS_PHE 0x00000020
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#define DPAA2_NI_FAS_BLE 0x00000010
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#define DPAA2_NI_FAS_L3CV 0x00000008 /* L3 csum validation performed */
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#define DPAA2_NI_FAS_L3CE 0x00000004 /* L3 csum error */
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#define DPAA2_NI_FAS_L4CV 0x00000002 /* L4 csum validation performed */
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#define DPAA2_NI_FAS_L4CE 0x00000001 /* L4 csum error */
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/* Mask for errors on the ingress path. */
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#define DPAA2_NI_FAS_RX_ERR_MASK (DPAA2_NI_FAS_KSE | \
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DPAA2_NI_FAS_EOFHE | \
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DPAA2_NI_FAS_MNLE | \
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DPAA2_NI_FAS_TIDE | \
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DPAA2_NI_FAS_PIEE | \
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DPAA2_NI_FAS_FLE | \
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DPAA2_NI_FAS_FPE | \
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DPAA2_NI_FAS_PTE | \
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DPAA2_NI_FAS_ISP | \
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DPAA2_NI_FAS_PHE | \
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DPAA2_NI_FAS_BLE | \
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DPAA2_NI_FAS_L3CE | \
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DPAA2_NI_FAS_L4CE \
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)
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/* Option bits to select specific queue configuration options to apply. */
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#define DPAA2_NI_QUEUE_OPT_USER_CTX 0x00000001
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#define DPAA2_NI_QUEUE_OPT_DEST 0x00000002
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#define DPAA2_NI_QUEUE_OPT_FLC 0x00000004
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#define DPAA2_NI_QUEUE_OPT_HOLD_ACTIVE 0x00000008
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#define DPAA2_NI_QUEUE_OPT_SET_CGID 0x00000040
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#define DPAA2_NI_QUEUE_OPT_CLEAR_CGID 0x00000080
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/* DPNI link configuration options. */
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#define DPAA2_NI_LINK_OPT_AUTONEG ((uint64_t) 0x01u)
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#define DPAA2_NI_LINK_OPT_HALF_DUPLEX ((uint64_t) 0x02u)
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#define DPAA2_NI_LINK_OPT_PAUSE ((uint64_t) 0x04u)
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#define DPAA2_NI_LINK_OPT_ASYM_PAUSE ((uint64_t) 0x08u)
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#define DPAA2_NI_LINK_OPT_PFC_PAUSE ((uint64_t) 0x10u)
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/*
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* Number of times to retry a frame enqueue before giving up. Value determined
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* empirically, in order to minimize the number of frames dropped on Tx.
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*/
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#define DPAA2_NI_ENQUEUE_RETRIES 10
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enum dpaa2_ni_queue_type {
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DPAA2_NI_QUEUE_RX = 0,
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DPAA2_NI_QUEUE_TX,
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DPAA2_NI_QUEUE_TX_CONF,
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DPAA2_NI_QUEUE_RX_ERR
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};
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enum dpaa2_ni_dest_type {
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DPAA2_NI_DEST_NONE = 0,
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DPAA2_NI_DEST_DPIO,
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DPAA2_NI_DEST_DPCON
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};
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enum dpaa2_ni_ofl_type {
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DPAA2_NI_OFL_RX_L3_CSUM = 0,
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DPAA2_NI_OFL_RX_L4_CSUM,
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DPAA2_NI_OFL_TX_L3_CSUM,
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DPAA2_NI_OFL_TX_L4_CSUM,
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DPAA2_NI_OFL_FLCTYPE_HASH /* FD flow context for AIOP/CTLU */
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};
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/**
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* @brief DPNI ingress traffic distribution mode.
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*/
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enum dpaa2_ni_dist_mode {
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DPAA2_NI_DIST_MODE_NONE = 0,
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DPAA2_NI_DIST_MODE_HASH,
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DPAA2_NI_DIST_MODE_FS
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};
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/**
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* @brief DPNI behavior in case of errors.
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*/
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enum dpaa2_ni_err_action {
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DPAA2_NI_ERR_DISCARD = 0,
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DPAA2_NI_ERR_CONTINUE,
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DPAA2_NI_ERR_SEND_TO_ERROR_QUEUE
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};
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struct dpaa2_ni_channel;
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struct dpaa2_ni_fq;
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/**
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* @brief Attributes of the DPNI object.
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*
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* options: ...
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* wriop_ver: Revision of the underlying WRIOP hardware block.
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*/
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struct dpaa2_ni_attr {
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uint32_t options;
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uint16_t wriop_ver;
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struct {
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uint16_t fs;
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uint8_t mac;
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uint8_t vlan;
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uint8_t qos;
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} entries;
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struct {
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uint8_t queues;
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uint8_t rx_tcs;
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uint8_t tx_tcs;
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uint8_t channels;
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uint8_t cgs;
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} num;
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struct {
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uint8_t fs;
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uint8_t qos;
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} key_size;
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};
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/**
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* @brief Tx ring.
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*
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* fq: Parent (TxConf) frame queue.
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* fqid: ID of the logical Tx queue.
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* mbuf_br: Ring buffer for mbufs to transmit.
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* mbuf_lock: Lock for the ring buffer.
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*/
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struct dpaa2_ni_tx_ring {
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struct dpaa2_ni_fq *fq;
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uint32_t fqid;
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uint32_t txid; /* Tx ring index */
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/* Ring buffer for indexes in "buf" array. */
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struct buf_ring *idx_br;
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struct mtx lock;
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/* Buffers to DMA load/unload Tx mbufs. */
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struct dpaa2_buf buf[DPAA2_NI_BUFS_PER_TX];
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};
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/**
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* @brief A Frame Queue is the basic queuing structure used by the QMan.
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*
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* It comprises a list of frame descriptors (FDs), so it can be thought of
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* as a queue of frames.
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*
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* NOTE: When frames on a FQ are ready to be processed, the FQ is enqueued
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* onto a work queue (WQ).
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*
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* fqid: Frame queue ID, can be used to enqueue/dequeue or execute other
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* commands on the queue through DPIO.
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* txq_n: Number of configured Tx queues.
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* tx_fqid: Frame queue IDs of the Tx queues which belong to the same flowid.
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* Note that Tx queues are logical queues and not all management
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* commands are available on these queue types.
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* qdbin: Queue destination bin. Can be used with the DPIO enqueue
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* operation based on QDID, QDBIN and QPRI. Note that all Tx queues
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* with the same flowid have the same destination bin.
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*/
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struct dpaa2_ni_fq {
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int (*consume)(struct dpaa2_ni_channel *,
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struct dpaa2_ni_fq *, struct dpaa2_fd *);
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struct dpaa2_ni_channel *chan;
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uint32_t fqid;
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uint16_t flowid;
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uint8_t tc;
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enum dpaa2_ni_queue_type type;
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/* Optional fields (for TxConf queue). */
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struct dpaa2_ni_tx_ring tx_rings[DPAA2_NI_MAX_TCS];
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uint32_t tx_qdbin;
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} __aligned(CACHE_LINE_SIZE);
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/**
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* @brief QBMan channel to process ingress traffic (Rx, Tx conf).
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*
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* NOTE: Several WQs are organized into a single WQ Channel.
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*/
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struct dpaa2_ni_channel {
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device_t ni_dev;
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device_t io_dev;
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device_t con_dev;
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uint16_t id;
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uint16_t flowid;
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/* For debug purposes only! */
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uint64_t tx_frames;
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uint64_t tx_dropped;
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/* Context to configure CDAN. */
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struct dpaa2_io_notif_ctx ctx;
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/* Channel storage (to keep responses from VDQ command). */
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struct dpaa2_buf store;
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uint32_t store_sz; /* in frames */
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uint32_t store_idx; /* frame index */
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/* Recycled buffers to release back to the pool. */
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uint32_t recycled_n;
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struct dpaa2_buf *recycled[DPAA2_SWP_BUFS_PER_CMD];
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/* Frame queues */
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uint32_t rxq_n;
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struct dpaa2_ni_fq rx_queues[DPAA2_NI_MAX_TCS];
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struct dpaa2_ni_fq txc_queue;
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};
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/**
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* @brief Configuration of the network interface queue.
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*
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* NOTE: This configuration is used to obtain information of a queue by
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* DPNI_GET_QUEUE command and update it by DPNI_SET_QUEUE one.
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*
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* It includes binding of the queue to a DPIO or DPCON object to receive
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* notifications and traffic on the CPU.
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*
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* user_ctx: (r/w) User defined data, presented along with the frames
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* being dequeued from this queue.
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* flow_ctx: (r/w) Set default FLC value for traffic dequeued from this queue.
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* Please check description of FD structure for more information.
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* Note that FLC values set using DPNI_ADD_FS_ENTRY, if any, take
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* precedence over values per queue.
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* dest_id: (r/w) The ID of a DPIO or DPCON object, depending on
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* DEST_TYPE (in flags) value. This field is ignored for DEST_TYPE
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* set to 0 (DPNI_DEST_NONE).
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* fqid: (r) Frame queue ID, can be used to enqueue/dequeue or execute
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* other commands on the queue through DPIO. Note that Tx queues
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* are logical queues and not all management commands are available
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* on these queue types.
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* qdbin: (r) Queue destination bin. Can be used with the DPIO enqueue
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* operation based on QDID, QDBIN and QPRI.
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* type: Type of the queue to set configuration to.
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* tc: Traffic class. Ignored for QUEUE_TYPE 2 and 3 (Tx confirmation
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* and Rx error queues).
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* idx: Selects a specific queue out of the set of queues in a TC.
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* Accepted values are in range 0 to NUM_QUEUES–1. This field is
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* ignored for QUEUE_TYPE 3 (Rx error queue). For access to the
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* shared Tx confirmation queue (for Tx confirmation mode 1), this
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* field must be set to 0xff.
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* cgid: (r/w) Congestion group ID.
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* chan_id: (w) Channel index to be configured. Used only when QUEUE_TYPE is
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* set to DPNI_QUEUE_TX.
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* priority: (r/w) Sets the priority in the destination DPCON or DPIO for
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* dequeued traffic. Supported values are 0 to # of priorities in
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* destination DPCON or DPIO - 1. This field is ignored for
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* DEST_TYPE set to 0 (DPNI_DEST_NONE), except if this DPNI is in
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* AIOP context. In that case the DPNI_SET_QUEUE can be used to
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* override the default assigned priority of the FQ from the TC.
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* options: Option bits selecting specific configuration options to apply.
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* See DPAA2_NI_QUEUE_OPT_* for details.
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* dest_type: Type of destination for dequeued traffic.
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* cgid_valid: (r) Congestion group ID is valid.
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* stash_control: (r/w) If true, lowest 6 bits of FLC are used for stash control.
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* Please check description of FD structure for more information.
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* hold_active: (r/w) If true, this flag prevents the queue from being
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* rescheduled between DPIOs while it carries traffic and is active
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* on one DPIO. Can help reduce reordering if one queue is services
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* on multiple CPUs, but the queue is also more likely to be trapped
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* in one DPIO, especially when congested.
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*/
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struct dpaa2_ni_queue_cfg {
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uint64_t user_ctx;
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uint64_t flow_ctx;
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uint32_t dest_id;
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uint32_t fqid;
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uint16_t qdbin;
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enum dpaa2_ni_queue_type type;
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uint8_t tc;
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uint8_t idx;
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uint8_t cgid;
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uint8_t chan_id;
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uint8_t priority;
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uint8_t options;
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enum dpaa2_ni_dest_type dest_type;
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bool cgid_valid;
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bool stash_control;
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bool hold_active;
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};
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/**
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* @brief Buffer layout attributes.
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*
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* pd_size: Size kept for private data (in bytes).
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* fd_align: Frame data alignment.
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* head_size: Data head room.
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* tail_size: Data tail room.
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* options: ...
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* pass_timestamp: Timestamp is included in the buffer layout.
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* pass_parser_result: Parsing results are included in the buffer layout.
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* pass_frame_status: Frame status is included in the buffer layout.
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* pass_sw_opaque: SW annotation is activated.
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* queue_type: Type of a queue this configuration applies to.
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*/
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struct dpaa2_ni_buf_layout {
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uint16_t pd_size;
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uint16_t fd_align;
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uint16_t head_size;
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uint16_t tail_size;
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uint16_t options;
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bool pass_timestamp;
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bool pass_parser_result;
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bool pass_frame_status;
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bool pass_sw_opaque;
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enum dpaa2_ni_queue_type queue_type;
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};
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/**
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* @brief Buffer pools configuration for a network interface.
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*/
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struct dpaa2_ni_pools_cfg {
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uint8_t pools_num;
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struct {
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uint32_t bp_obj_id;
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uint16_t buf_sz;
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int backup_flag; /* 0 - regular pool, 1 - backup pool */
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} pools[DPAA2_NI_MAX_POOLS];
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};
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/**
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* @brief Errors behavior configuration for a network interface.
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*
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* err_mask: The errors mask to configure.
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* action: Desired action for the errors selected in the mask.
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* set_err_fas: Set to true to mark the errors in frame annotation
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* status (FAS); relevant for non-discard actions only.
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*/
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struct dpaa2_ni_err_cfg {
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uint32_t err_mask;
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enum dpaa2_ni_err_action action;
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bool set_err_fas;
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};
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/**
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* @brief Link configuration.
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*
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* options: Mask of available options.
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* adv_speeds: Speeds that are advertised for autoneg.
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* rate: Rate in Mbps.
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*/
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struct dpaa2_ni_link_cfg {
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uint64_t options;
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uint64_t adv_speeds;
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uint32_t rate;
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};
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/**
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* @brief Link state.
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*
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* options: Mask of available options.
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* adv_speeds: Speeds that are advertised for autoneg.
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* sup_speeds: Speeds capability of the PHY.
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* rate: Rate in Mbps.
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* link_up: Link state (true if link is up, false otherwise).
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* state_valid: Ignore/Update the state of the link.
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*/
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struct dpaa2_ni_link_state {
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uint64_t options;
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||
uint64_t adv_speeds;
|
||
uint64_t sup_speeds;
|
||
uint32_t rate;
|
||
bool link_up;
|
||
bool state_valid;
|
||
};
|
||
|
||
/**
|
||
* @brief QoS table configuration.
|
||
*
|
||
* kcfg_busaddr: Address of the buffer in I/O virtual address space which
|
||
* holds the QoS table key configuration.
|
||
* default_tc: Default traffic class to use in case of a lookup miss in
|
||
* the QoS table.
|
||
* discard_on_miss: Set to true to discard frames in case of no match.
|
||
* Default traffic class will be used otherwise.
|
||
* keep_entries: Set to true to keep existing QoS table entries. This
|
||
* option will work properly only for DPNI objects created
|
||
* with DPNI_OPT_HAS_KEY_MASKING option.
|
||
*/
|
||
struct dpaa2_ni_qos_table {
|
||
uint64_t kcfg_busaddr;
|
||
uint8_t default_tc;
|
||
bool discard_on_miss;
|
||
bool keep_entries;
|
||
};
|
||
|
||
/**
|
||
* @brief Context to add multicast physical addresses to the filter table.
|
||
*
|
||
* ifp: Network interface associated with the context.
|
||
* error: Result of the last MC command.
|
||
* nent: Number of entries added.
|
||
*/
|
||
struct dpaa2_ni_mcaddr_ctx {
|
||
struct ifnet *ifp;
|
||
int error;
|
||
int nent;
|
||
};
|
||
|
||
struct dpaa2_eth_dist_fields {
|
||
uint64_t rxnfc_field;
|
||
enum net_prot cls_prot;
|
||
int cls_field;
|
||
int size;
|
||
uint64_t id;
|
||
};
|
||
|
||
struct dpni_mask_cfg {
|
||
uint8_t mask;
|
||
uint8_t offset;
|
||
} __packed;
|
||
|
||
struct dpni_dist_extract {
|
||
uint8_t prot;
|
||
uint8_t efh_type; /* EFH type is in the 4 LSBs. */
|
||
uint8_t size;
|
||
uint8_t offset;
|
||
uint32_t field;
|
||
uint8_t hdr_index;
|
||
uint8_t constant;
|
||
uint8_t num_of_repeats;
|
||
uint8_t num_of_byte_masks;
|
||
uint8_t extract_type; /* Extraction type is in the 4 LSBs */
|
||
uint8_t _reserved[3];
|
||
struct dpni_mask_cfg masks[4];
|
||
} __packed;
|
||
|
||
struct dpni_ext_set_rx_tc_dist {
|
||
uint8_t num_extracts;
|
||
uint8_t _reserved[7];
|
||
struct dpni_dist_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
|
||
} __packed;
|
||
|
||
/**
|
||
* @brief Software context for the DPAA2 Network Interface driver.
|
||
*/
|
||
struct dpaa2_ni_softc {
|
||
device_t dev;
|
||
struct resource *res[DPAA2_NI_MAX_RESOURCES];
|
||
uint16_t api_major;
|
||
uint16_t api_minor;
|
||
uint64_t rx_hash_fields;
|
||
uint16_t tx_data_off;
|
||
uint16_t tx_qdid;
|
||
uint32_t link_options;
|
||
int link_state;
|
||
|
||
uint16_t buf_align;
|
||
uint16_t buf_sz;
|
||
|
||
/* For debug purposes only! */
|
||
uint64_t rx_anomaly_frames;
|
||
uint64_t rx_single_buf_frames;
|
||
uint64_t rx_sg_buf_frames;
|
||
uint64_t rx_enq_rej_frames;
|
||
uint64_t rx_ieoi_err_frames;
|
||
uint64_t tx_single_buf_frames;
|
||
uint64_t tx_sg_frames;
|
||
|
||
/* Attributes of the DPAA2 network interface. */
|
||
struct dpaa2_ni_attr attr;
|
||
|
||
/* For network interface and miibus. */
|
||
struct ifnet *ifp;
|
||
uint32_t if_flags;
|
||
struct mtx lock;
|
||
device_t miibus;
|
||
struct mii_data *mii;
|
||
bool fixed_link;
|
||
struct ifmedia fixed_ifmedia;
|
||
int media_status;
|
||
|
||
/* DMA resources */
|
||
bus_dma_tag_t bp_dmat; /* for buffer pool */
|
||
bus_dma_tag_t tx_dmat; /* for Tx buffers */
|
||
bus_dma_tag_t st_dmat; /* for channel storage */
|
||
bus_dma_tag_t rxd_dmat; /* for Rx distribution key */
|
||
bus_dma_tag_t qos_dmat; /* for QoS table key */
|
||
bus_dma_tag_t sgt_dmat; /* for scatter/gather tables */
|
||
|
||
struct dpaa2_buf qos_kcfg; /* QoS table key config. */
|
||
struct dpaa2_buf rxd_kcfg; /* Rx distribution key config. */
|
||
|
||
/* Channels and RxError frame queue */
|
||
uint32_t chan_n;
|
||
struct dpaa2_ni_channel *channels[DPAA2_NI_MAX_CHANNELS];
|
||
struct dpaa2_ni_fq rxe_queue; /* one per network interface */
|
||
|
||
/* Rx buffers for buffer pool. */
|
||
struct dpaa2_atomic buf_num;
|
||
struct dpaa2_atomic buf_free; /* for sysctl(9) only */
|
||
struct dpaa2_buf buf[DPAA2_NI_BUFS_MAX];
|
||
|
||
/* Interrupts */
|
||
int irq_rid[DPAA2_NI_MSI_COUNT];
|
||
struct resource *irq_res;
|
||
void *intr; /* interrupt handle */
|
||
|
||
/* Tasks */
|
||
struct taskqueue *bp_taskq;
|
||
struct task bp_task;
|
||
|
||
/* Callouts */
|
||
struct callout mii_callout;
|
||
|
||
struct {
|
||
uint32_t dpmac_id;
|
||
uint8_t addr[ETHER_ADDR_LEN];
|
||
device_t phy_dev;
|
||
int phy_loc;
|
||
} mac; /* Info about connected DPMAC (if exists). */
|
||
};
|
||
|
||
extern struct resource_spec dpaa2_ni_spec[];
|
||
|
||
#endif /* _DPAA2_NI_H */
|