517904de5c
This controller supports 2.5G/1G/100MB/10MB speeds, and allows
tx/rx checksum offload, TSO, LRO, and multi-queue operation.
The driver was derived from code contributed by Intel, and modified
by Netgate to fit into the iflib framework.
Thanks to Mike Karels for testing and feedback on the driver.
Reviewed by: bcr (manpages), kbowling, scottl, erj
MFC after: 1 month
Relnotes: yes
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D30668
49 lines
2.0 KiB
C
49 lines
2.0 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* $FreeBSD$
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*/
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#ifndef _IGC_MAC_H_
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#define _IGC_MAC_H_
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void igc_init_mac_ops_generic(struct igc_hw *hw);
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void igc_null_mac_generic(struct igc_hw *hw);
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s32 igc_null_ops_generic(struct igc_hw *hw);
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s32 igc_null_link_info(struct igc_hw *hw, u16 *s, u16 *d);
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bool igc_null_mng_mode(struct igc_hw *hw);
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void igc_null_update_mc(struct igc_hw *hw, u8 *h, u32 a);
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void igc_null_write_vfta(struct igc_hw *hw, u32 a, u32 b);
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int igc_null_rar_set(struct igc_hw *hw, u8 *h, u32 a);
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s32 igc_check_for_copper_link_generic(struct igc_hw *hw);
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s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw);
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s32 igc_disable_pcie_master_generic(struct igc_hw *hw);
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s32 igc_force_mac_fc_generic(struct igc_hw *hw);
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s32 igc_get_auto_rd_done_generic(struct igc_hw *hw);
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s32 igc_get_bus_info_pcie_generic(struct igc_hw *hw);
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void igc_set_lan_id_single_port(struct igc_hw *hw);
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s32 igc_get_hw_semaphore_generic(struct igc_hw *hw);
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s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed,
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u16 *duplex);
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void igc_update_mc_addr_list_generic(struct igc_hw *hw,
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u8 *mc_addr_list, u32 mc_addr_count);
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int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index);
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s32 igc_set_fc_watermarks_generic(struct igc_hw *hw);
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s32 igc_setup_link_generic(struct igc_hw *hw);
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s32 igc_validate_mdi_setting_crossover_generic(struct igc_hw *hw);
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u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr);
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void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw);
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void igc_clear_vfta_generic(struct igc_hw *hw);
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void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count);
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void igc_pcix_mmrbc_workaround_generic(struct igc_hw *hw);
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void igc_put_hw_semaphore_generic(struct igc_hw *hw);
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s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw);
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void igc_set_pcie_no_snoop_generic(struct igc_hw *hw, u32 no_snoop);
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void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value);
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#endif
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