Teach the pci host generic ACPI attachment about PCI_ID_OFW_IOMMU. This will be used by the arm64 smmu IOMMU driver to read the xref and ID this interface provides in a bus-agnostic way. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D39182
537 lines
14 KiB
C
537 lines
14 KiB
C
/*-
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* Copyright (C) 2018 Cavium Inc.
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2014 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Generic ECAM PCIe driver */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/rman.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/cpuset.h>
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#include <sys/rwlock.h>
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#include <contrib/dev/acpica/include/acpi.h>
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#include <contrib/dev/acpica/include/accommon.h>
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#include <dev/acpica/acpivar.h>
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#include <dev/acpica/acpi_pcibvar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <dev/pci/pci_host_generic.h>
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#include <dev/pci/pci_host_generic_acpi.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include "pcib_if.h"
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#include "acpi_bus_if.h"
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/* Assembling ECAM Configuration Address */
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#define PCIE_BUS_SHIFT 20
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#define PCIE_SLOT_SHIFT 15
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#define PCIE_FUNC_SHIFT 12
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#define PCIE_BUS_MASK 0xFF
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#define PCIE_SLOT_MASK 0x1F
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#define PCIE_FUNC_MASK 0x07
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#define PCIE_REG_MASK 0xFFF
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#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
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((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
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(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
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(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
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((reg) & PCIE_REG_MASK))
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#define PCI_IO_WINDOW_OFFSET 0x1000
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#define SPACE_CODE_SHIFT 24
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#define SPACE_CODE_MASK 0x3
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#define SPACE_CODE_IO_SPACE 0x1
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#define PROPS_CELL_SIZE 1
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#define PCI_ADDR_CELL_SIZE 2
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static struct {
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char oem_id[ACPI_OEM_ID_SIZE + 1];
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char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
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uint32_t quirks;
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} pci_acpi_quirks[] = {
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{ "MRVL ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK },
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{ "MRVL ", "CN913X ", PCIE_ECAM_DESIGNWARE_QUIRK },
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{ "MVEBU ", "ARMADA7K", PCIE_ECAM_DESIGNWARE_QUIRK },
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{ "MVEBU ", "ARMADA8K", PCIE_ECAM_DESIGNWARE_QUIRK },
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{ "MVEBU ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK },
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{ "MVEBU ", "CN9131 ", PCIE_ECAM_DESIGNWARE_QUIRK },
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{ "MVEBU ", "CN9132 ", PCIE_ECAM_DESIGNWARE_QUIRK },
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{ 0 },
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};
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/* Forward prototypes */
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static int generic_pcie_acpi_probe(device_t dev);
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static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *);
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static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);
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/*
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* generic_pcie_acpi_probe - look for root bridge flag
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*/
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static int
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generic_pcie_acpi_probe(device_t dev)
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{
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ACPI_DEVICE_INFO *devinfo;
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ACPI_HANDLE h;
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int root;
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if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
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ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
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return (ENXIO);
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root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
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AcpiOsFree(devinfo);
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if (!root)
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return (ENXIO);
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device_set_desc(dev, "Generic PCI host controller");
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return (BUS_PROBE_GENERIC);
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}
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/*
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* pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
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* 'produced' by this bridge
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*/
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static ACPI_STATUS
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pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg)
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{
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device_t dev = (device_t)arg;
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struct generic_pcie_acpi_softc *sc;
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rman_res_t min, max, off;
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int r, restype;
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sc = device_get_softc(dev);
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r = sc->base.nranges;
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switch (res->Type) {
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case ACPI_RESOURCE_TYPE_ADDRESS16:
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restype = res->Data.Address16.ResourceType;
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min = res->Data.Address16.Address.Minimum;
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max = res->Data.Address16.Address.Maximum;
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break;
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case ACPI_RESOURCE_TYPE_ADDRESS32:
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restype = res->Data.Address32.ResourceType;
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min = res->Data.Address32.Address.Minimum;
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max = res->Data.Address32.Address.Maximum;
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off = res->Data.Address32.Address.TranslationOffset;
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break;
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case ACPI_RESOURCE_TYPE_ADDRESS64:
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restype = res->Data.Address64.ResourceType;
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min = res->Data.Address64.Address.Minimum;
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max = res->Data.Address64.Address.Maximum;
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off = res->Data.Address64.Address.TranslationOffset;
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break;
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case ACPI_RESOURCE_TYPE_FIXED_MEMORY32:
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/*
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* The Microsoft Dev Kit 2023 uses a fixed memory region
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* for some PCI controllers. For this memory the
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* ResourceType is ACPI_IO_RANGE meaning we create an IO
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* resource. As drivers expect it to be a memory resource
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* force the type here.
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*/
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restype = ACPI_MEMORY_RANGE;
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min = res->Data.FixedMemory32.Address;
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max = res->Data.FixedMemory32.Address +
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res->Data.FixedMemory32.AddressLength - 1;
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off = 0;
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break;
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default:
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return (AE_OK);
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}
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/* Save detected ranges */
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if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE ||
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res->Data.Address.ResourceType == ACPI_IO_RANGE) {
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sc->base.ranges[r].pci_base = min;
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sc->base.ranges[r].phys_base = min + off;
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sc->base.ranges[r].size = max - min + 1;
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if (restype == ACPI_MEMORY_RANGE)
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sc->base.ranges[r].flags |= FLAG_TYPE_MEM;
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else if (restype == ACPI_IO_RANGE)
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sc->base.ranges[r].flags |= FLAG_TYPE_IO;
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sc->base.nranges++;
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} else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) {
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sc->base.bus_start = min;
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sc->base.bus_end = max;
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}
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return (AE_OK);
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}
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static void
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pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc *sc,
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ACPI_TABLE_HEADER *hdr)
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{
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int i;
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for (i = 0; pci_acpi_quirks[i].quirks; i++) {
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if (memcmp(hdr->OemId, pci_acpi_quirks[i].oem_id,
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ACPI_OEM_ID_SIZE) != 0)
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continue;
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if (memcmp(hdr->OemTableId, pci_acpi_quirks[i].oem_table_id,
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ACPI_OEM_TABLE_ID_SIZE) != 0)
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continue;
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sc->base.quirks |= pci_acpi_quirks[i].quirks;
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}
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}
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static int
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pci_host_acpi_get_ecam_resource(device_t dev)
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{
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struct generic_pcie_acpi_softc *sc;
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struct acpi_device *ad;
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struct resource_list *rl;
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ACPI_TABLE_HEADER *hdr;
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ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end;
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ACPI_HANDLE handle;
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ACPI_STATUS status;
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rman_res_t base, start, end;
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int found, val;
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sc = device_get_softc(dev);
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handle = acpi_get_handle(dev);
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/* Try MCFG first */
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status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
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if (ACPI_SUCCESS(status)) {
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found = FALSE;
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mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
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mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
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while (mcfg_entry < mcfg_end && !found) {
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if (mcfg_entry->PciSegment == sc->base.ecam &&
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mcfg_entry->StartBusNumber <= sc->base.bus_start &&
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mcfg_entry->EndBusNumber >= sc->base.bus_start)
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found = TRUE;
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else
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mcfg_entry++;
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}
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if (found) {
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if (mcfg_entry->EndBusNumber < sc->base.bus_end)
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sc->base.bus_end = mcfg_entry->EndBusNumber;
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base = mcfg_entry->Address;
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} else {
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device_printf(dev, "MCFG exists, but does not have bus %d-%d\n",
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sc->base.bus_start, sc->base.bus_end);
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return (ENXIO);
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}
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pci_host_acpi_get_oem_quirks(sc, hdr);
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if (sc->base.quirks & PCIE_ECAM_DESIGNWARE_QUIRK)
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device_set_desc(dev, "Synopsys DesignWare PCIe Controller");
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} else {
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status = acpi_GetInteger(handle, "_CBA", &val);
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if (ACPI_SUCCESS(status))
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base = val;
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else
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return (ENXIO);
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}
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/* add as MEM rid 0 */
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ad = device_get_ivars(dev);
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rl = &ad->ad_rl;
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start = base + (sc->base.bus_start << PCIE_BUS_SHIFT);
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end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1;
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resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1);
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if (bootverbose)
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device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n",
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sc->base.bus_start, sc->base.bus_end, start, end);
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return (0);
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}
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int
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pci_host_generic_acpi_init(device_t dev)
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{
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struct generic_pcie_acpi_softc *sc;
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ACPI_HANDLE handle;
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ACPI_STATUS status;
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int error;
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sc = device_get_softc(dev);
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handle = acpi_get_handle(dev);
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/* Get Start bus number for the PCI host bus is from _BBN method */
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status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start);
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if (ACPI_FAILURE(status)) {
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device_printf(dev, "No _BBN, using start bus 0\n");
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sc->base.bus_start = 0;
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}
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sc->base.bus_end = 255;
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/* Get PCI Segment (domain) needed for MCFG lookup */
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status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam);
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if (ACPI_FAILURE(status)) {
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device_printf(dev, "No _SEG for PCI Bus, using segment 0\n");
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sc->base.ecam = 0;
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}
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/* Bus decode ranges */
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status = AcpiWalkResources(handle, "_CRS",
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pci_host_generic_acpi_parse_resource, (void *)dev);
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if (ACPI_FAILURE(status))
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return (ENXIO);
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/* Coherency attribute */
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if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
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sc->base.coherent = 0;
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if (bootverbose)
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device_printf(dev, "Bus is%s cache-coherent\n",
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sc->base.coherent ? "" : " not");
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/* add config space resource */
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pci_host_acpi_get_ecam_resource(dev);
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acpi_pcib_fetch_prt(dev, &sc->ap_prt);
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error = pci_host_generic_core_attach(dev);
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if (error != 0)
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return (error);
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return (0);
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}
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static int
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pci_host_generic_acpi_attach(device_t dev)
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{
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int error;
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error = pci_host_generic_acpi_init(dev);
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if (error != 0)
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return (error);
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static int
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generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
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uintptr_t *result)
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{
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struct generic_pcie_acpi_softc *sc;
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sc = device_get_softc(dev);
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if (index == PCIB_IVAR_BUS) {
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*result = sc->base.bus_start;
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return (0);
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}
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if (index == PCIB_IVAR_DOMAIN) {
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*result = sc->base.ecam;
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return (0);
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}
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if (bootverbose)
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device_printf(dev, "ERROR: Unknown index %d.\n", index);
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return (ENOENT);
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}
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static int
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generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)
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{
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struct generic_pcie_acpi_softc *sc;
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sc = device_get_softc(bus);
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return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));
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}
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static u_int
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generic_pcie_get_xref(device_t pci, device_t child)
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{
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struct generic_pcie_acpi_softc *sc;
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uintptr_t rid;
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u_int xref, devid;
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int err;
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sc = device_get_softc(pci);
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err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
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if (err != 0)
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return (ACPI_MSI_XREF);
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err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
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if (err != 0)
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return (ACPI_MSI_XREF);
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return (xref);
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}
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static u_int
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generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id)
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{
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struct generic_pcie_acpi_softc *sc;
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uintptr_t rid;
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u_int xref, devid;
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int err;
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sc = device_get_softc(pci);
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err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
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if (err != 0)
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return (err);
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err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
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if (err == 0)
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*id = devid;
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else
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*id = rid; /* RID not in IORT, likely FW bug, ignore */
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return (0);
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}
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static int
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generic_pcie_get_iommu(device_t pci, device_t child, uintptr_t *id)
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{
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struct generic_pcie_acpi_softc *sc;
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struct pci_id_ofw_iommu *iommu;
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u_int iommu_sid, iommu_xref;
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uintptr_t rid;
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int err;
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iommu = (struct pci_id_ofw_iommu *)id;
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sc = device_get_softc(pci);
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err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
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if (err != 0)
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return (err);
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err = acpi_iort_map_pci_smmuv3(sc->base.ecam, rid, &iommu_xref,
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&iommu_sid);
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if (err == 0) {
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iommu->id = iommu_sid;
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iommu->xref = iommu_xref;
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}
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return (err);
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}
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static int
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generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,
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int maxcount, int *irqs)
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{
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#if defined(INTRNG)
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return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child),
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count, maxcount, irqs));
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#else
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return (ENXIO);
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#endif
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}
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static int
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generic_pcie_acpi_release_msi(device_t pci, device_t child, int count,
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int *irqs)
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{
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#if defined(INTRNG)
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return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child),
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count, irqs));
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#else
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return (ENXIO);
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#endif
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}
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static int
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generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
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uint32_t *data)
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{
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#if defined(INTRNG)
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return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq,
|
|
addr, data));
|
|
#else
|
|
return (ENXIO);
|
|
#endif
|
|
}
|
|
|
|
static int
|
|
generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq)
|
|
{
|
|
|
|
#if defined(INTRNG)
|
|
return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child),
|
|
irq));
|
|
#else
|
|
return (ENXIO);
|
|
#endif
|
|
}
|
|
|
|
static int
|
|
generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq)
|
|
{
|
|
|
|
#if defined(INTRNG)
|
|
return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child),
|
|
irq));
|
|
#else
|
|
return (ENXIO);
|
|
#endif
|
|
}
|
|
|
|
static int
|
|
generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,
|
|
uintptr_t *id)
|
|
{
|
|
if (type == PCI_ID_OFW_IOMMU)
|
|
return (generic_pcie_get_iommu(pci, child, id));
|
|
|
|
if (type == PCI_ID_MSI)
|
|
return (generic_pcie_map_id(pci, child, id));
|
|
|
|
return (pcib_get_id(pci, child, type, id));
|
|
}
|
|
|
|
static device_method_t generic_pcie_acpi_methods[] = {
|
|
DEVMETHOD(device_probe, generic_pcie_acpi_probe),
|
|
DEVMETHOD(device_attach, pci_host_generic_acpi_attach),
|
|
DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),
|
|
DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi),
|
|
DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi),
|
|
DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix),
|
|
DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix),
|
|
DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi),
|
|
DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods,
|
|
sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver);
|
|
|
|
DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, 0, 0);
|