48a7e53db7
To simplify adding new handlers merge the common parts of the functions used to call into the arm SMCCC firmware. Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D36297
62 lines
2.2 KiB
ArmAsm
62 lines
2.2 KiB
ArmAsm
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2015 Andrew Turner
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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.arch_extension sec /* For smc */
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.arch_extension virt /* For hvc */
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.macro arm_smccc_1_0 insn
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ENTRY(arm_smccc_\insn)
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mov r12, sp
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push {r4-r7}
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ldm r12, {r4-r7}
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\insn #0
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pop {r4-r7}
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ldr r12, [sp, #(4 * 4)]
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cmp r12, #0
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beq 1f
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stm r12, {r0-r3}
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1: bx lr
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END(arm_smccc_\insn)
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.endm
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/*
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* int arm_smccc_hvc(register_t, register_t, register_t, register_t,
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* register_t, register_t, register_t, register_t,
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* struct arm_smccc_res *res)
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*/
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arm_smccc_1_0 hvc
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arm_smccc_1_0 smc
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