e34a491b35
These clock nodes are used by the IPQ4018/IPQ4019 and derivatives. They're also used by other 32 and 64 bit qualcomm parts; so it's best to put these nodes here in a single qcom_clk driver and add to it as we grow new Qualcomm SoC support. Tested: * IPQ4018, boot Differential Revision: https://reviews.freebsd.org/D33665
59 lines
2.4 KiB
C
59 lines
2.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QCOM_CLK_RCG2_REG_H__
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#define __QCOM_CLK_RCG2_REG_H__
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#define QCOM_CLK_RCG2_CMD_REG 0x0
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#define QCOM_CLK_RCG2_CMD_UPDATE (1U << 0)
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#define QCOM_CLK_RCG2_CMD_ROOT_EN (1U << 1)
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#define QCOM_CLK_RCG2_CMD_DIRTY_CFG (1U << 4)
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#define QCOM_CLK_RCG2_CMD_DIRTY_N (1U << 5)
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#define QCOM_CLK_RCG2_CMD_DIRTY_M (1U << 6)
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#define QCOM_CLK_RCG2_CMD_DIRTY_D (1U << 7)
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#define QCOM_CLK_RCG2_CMD_ROOT_OFF (1U << 31)
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#define QCOM_CLK_RCG2_CFG_REG 0x4
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#define QCOM_CLK_RCG2_CFG_SRC_DIV_SHIFT 0
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#define QCOM_CLK_RCG2_CFG_SRC_SEL_SHIFT 8
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#define QCOM_CLK_RCG2_CFG_SRC_SEL_MASK \
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(0x7 << QCOM_CLK_RCG2_CFG_SRC_SEL_SHIFT)
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#define QCOM_CLK_RCG2_CFG_MODE_SHIFT 12
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#define QCOM_CLK_RCG2_CFG_MODE_MASK \
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(0x3 << QCOM_CLK_RCG2_CFG_MODE_SHIFT)
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#define QCOM_CLK_RCG2_CFG_MODE_DUAL_EDGE \
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(0x2 << QCOM_CLK_RCG2_CFG_MODE_SHIFT)
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#define QCOM_CLK_RCG2_CFG_HW_CLK_CTRL_MASK (1U << 20)
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#define QCOM_CLK_RCG2_M_REG 0x8
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#define QCOM_CLK_RCG2_N_REG 0xc
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#define QCOM_CLK_RCG2_D_REG 0x10
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#endif /* __QCOM_CLK_RCG2_REG_H__ */
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