699 lines
19 KiB
C
699 lines
19 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2012 Thomas Skibo
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* Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Generic driver to attach sdhci controllers on simplebus.
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* Derived mainly from sdhci_pci.c
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/syscon/syscon.h>
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#include <dev/extres/phy/phy.h>
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#include <dev/mmc/bridge.h>
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#include <dev/sdhci/sdhci.h>
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#include "mmcbr_if.h"
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#include "sdhci_if.h"
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#include "opt_mmccam.h"
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#include "clkdev_if.h"
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#include "syscon_if.h"
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#define MAX_SLOTS 6
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#define SDHCI_FDT_ARMADA38X 1
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#define SDHCI_FDT_GENERIC 2
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#define SDHCI_FDT_XLNX_ZY7 3
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#define SDHCI_FDT_QUALCOMM 4
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#define SDHCI_FDT_RK3399 5
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#define SDHCI_FDT_RK3568 6
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#define RK3399_GRF_EMMCCORE_CON0 0xf000
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#define RK3399_CORECFG_BASECLKFREQ 0xff00
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#define RK3399_CORECFG_TIMEOUTCLKUNIT (1 << 7)
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#define RK3399_CORECFG_TUNINGCOUNT 0x3f
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#define RK3399_GRF_EMMCCORE_CON11 0xf02c
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#define RK3399_CORECFG_CLOCKMULTIPLIER 0xff
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#define RK3568_EMMC_HOST_CTRL 0x0508
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#define RK3568_EMMC_EMMC_CTRL 0x052c
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#define RK3568_EMMC_ATCTRL 0x0540
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#define RK3568_EMMC_DLL_CTRL 0x0800
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#define DLL_CTRL_SRST 0x00000001
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#define DLL_CTRL_START 0x00000002
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#define DLL_CTRL_START_POINT_DEFAULT 0x00050000
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#define DLL_CTRL_INCREMENT_DEFAULT 0x00000200
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#define RK3568_EMMC_DLL_RXCLK 0x0804
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#define DLL_RXCLK_DELAY_ENABLE 0x08000000
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#define DLL_RXCLK_NO_INV 0x20000000
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#define RK3568_EMMC_DLL_TXCLK 0x0808
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#define DLL_TXCLK_DELAY_ENABLE 0x08000000
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#define DLL_TXCLK_TAPNUM_DEFAULT 0x00000008
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#define DLL_TXCLK_TAPNUM_FROM_SW 0x01000000
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#define RK3568_EMMC_DLL_STRBIN 0x080c
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#define DLL_STRBIN_DELAY_ENABLE 0x08000000
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#define DLL_STRBIN_TAPNUM_DEFAULT 0x00000008
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#define DLL_STRBIN_TAPNUM_FROM_SW 0x01000000
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#define RK3568_EMMC_DLL_STATUS0 0x0840
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#define DLL_STATUS0_DLL_LOCK 0x00000100
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#define DLL_STATUS0_DLL_TIMEOUT 0x00000200
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#define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
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#define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask))
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#define EMMCCARDCLK_ID 1000
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static struct ofw_compat_data compat_data[] = {
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{ "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X },
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{ "sdhci_generic", SDHCI_FDT_GENERIC },
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{ "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM },
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{ "rockchip,rk3399-sdhci-5.1", SDHCI_FDT_RK3399 },
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{ "xlnx,zy7_sdhci", SDHCI_FDT_XLNX_ZY7 },
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{ "rockchip,rk3568-dwcmshc", SDHCI_FDT_RK3568 },
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{ NULL, 0 }
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};
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struct sdhci_fdt_softc {
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device_t dev; /* Controller device */
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u_int quirks; /* Chip specific quirks */
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u_int caps; /* If we override SDHCI_CAPABILITIES */
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uint32_t max_clk; /* Max possible freq */
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uint8_t sdma_boundary; /* If we override the SDMA boundary */
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struct resource *irq_res; /* IRQ resource */
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void *intrhand; /* Interrupt handle */
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int num_slots; /* Number of slots on this controller*/
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struct sdhci_slot slots[MAX_SLOTS];
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struct resource *mem_res[MAX_SLOTS]; /* Memory resource */
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bool wp_inverted; /* WP pin is inverted */
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bool no_18v; /* No 1.8V support */
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clk_t clk_xin; /* xin24m fixed clock */
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clk_t clk_ahb; /* ahb clock */
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clk_t clk_core; /* core clock */
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phy_t phy; /* phy to be used */
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};
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struct rk3399_emmccardclk_sc {
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device_t clkdev;
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bus_addr_t reg;
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};
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static int
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rk3399_emmccardclk_init(struct clknode *clk, device_t dev)
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{
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static clknode_method_t rk3399_emmccardclk_clknode_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, rk3399_emmccardclk_init),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(rk3399_emmccardclk_clknode, rk3399_emmccardclk_clknode_class,
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rk3399_emmccardclk_clknode_methods, sizeof(struct rk3399_emmccardclk_sc),
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clknode_class);
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static int
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rk3399_ofw_map(struct clkdom *clkdom, uint32_t ncells,
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phandle_t *cells, struct clknode **clk)
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{
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if (ncells == 0)
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*clk = clknode_find_by_id(clkdom, EMMCCARDCLK_ID);
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else
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return (ERANGE);
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if (*clk == NULL)
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return (ENXIO);
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return (0);
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}
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static void
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sdhci_init_rk3399_emmccardclk(device_t dev)
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{
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struct clknode_init_def def;
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struct rk3399_emmccardclk_sc *sc;
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struct clkdom *clkdom;
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struct clknode *clk;
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clk_t clk_parent;
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bus_addr_t paddr;
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bus_size_t psize;
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const char **clknames;
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phandle_t node;
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int i, nclocks, ncells, error;
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node = ofw_bus_get_node(dev);
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if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
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device_printf(dev, "cannot parse 'reg' property\n");
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return;
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}
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error = ofw_bus_parse_xref_list_get_length(node, "clocks",
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"#clock-cells", &ncells);
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if (error != 0 || ncells != 2) {
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device_printf(dev, "couldn't find parent clocks\n");
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return;
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}
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nclocks = ofw_bus_string_list_to_array(node, "clock-output-names",
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&clknames);
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/* No clocks to export */
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if (nclocks <= 0)
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return;
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if (nclocks != 1) {
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device_printf(dev, "Having %d clock instead of 1, aborting\n",
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nclocks);
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return;
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}
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clkdom = clkdom_create(dev);
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clkdom_set_ofw_mapper(clkdom, rk3399_ofw_map);
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memset(&def, 0, sizeof(def));
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def.id = EMMCCARDCLK_ID;
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def.name = clknames[0];
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def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
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for (i = 0; i < ncells; i++) {
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error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
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if (error != 0) {
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device_printf(dev, "cannot get clock %d\n", error);
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return;
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}
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def.parent_names[i] = clk_get_name(clk_parent);
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if (bootverbose)
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device_printf(dev, "clk parent: %s\n",
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def.parent_names[i]);
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clk_release(clk_parent);
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}
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def.parent_cnt = ncells;
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clk = clknode_create(clkdom, &rk3399_emmccardclk_clknode_class, &def);
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if (clk == NULL) {
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device_printf(dev, "cannot create clknode\n");
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return;
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}
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sc = clknode_get_softc(clk);
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sc->reg = paddr;
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sc->clkdev = device_get_parent(dev);
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clknode_register(clkdom, clk);
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if (clkdom_finit(clkdom) != 0) {
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device_printf(dev, "cannot finalize clkdom initialization\n");
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return;
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}
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if (bootverbose)
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clkdom_dump(clkdom);
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}
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static int
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sdhci_init_rk3399(device_t dev)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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struct syscon *grf = NULL;
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phandle_t node;
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uint64_t freq;
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uint32_t mask, val;
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int error;
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/* Get and activate clocks */
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error = clk_get_by_ofw_name(dev, 0, "clk_xin", &sc->clk_xin);
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if (error != 0) {
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device_printf(dev, "cannot get xin clock\n");
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return (ENXIO);
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}
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error = clk_enable(sc->clk_xin);
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if (error != 0) {
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device_printf(dev, "cannot enable xin clock\n");
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return (ENXIO);
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}
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error = clk_get_freq(sc->clk_xin, &freq);
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if (error != 0) {
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device_printf(dev, "cannot get xin clock frequency\n");
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return (ENXIO);
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}
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error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb);
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if (error != 0) {
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device_printf(dev, "cannot get ahb clock\n");
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return (ENXIO);
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}
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error = clk_enable(sc->clk_ahb);
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if (error != 0) {
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device_printf(dev, "cannot enable ahb clock\n");
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return (ENXIO);
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}
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/* Register clock */
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sdhci_init_rk3399_emmccardclk(dev);
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/* Enable PHY */
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error = phy_get_by_ofw_name(dev, 0, "phy_arasan", &sc->phy);
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if (error != 0) {
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device_printf(dev, "Could not get phy\n");
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return (ENXIO);
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}
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error = phy_enable(sc->phy);
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if (error != 0) {
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device_printf(dev, "Could not enable phy\n");
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return (ENXIO);
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}
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/* Get syscon */
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node = ofw_bus_get_node(dev);
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if (OF_hasprop(node, "arasan,soc-ctl-syscon") &&
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syscon_get_by_ofw_property(dev, node,
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"arasan,soc-ctl-syscon", &grf) != 0) {
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device_printf(dev, "cannot get grf driver handle\n");
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return (ENXIO);
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}
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/* Disable clock multiplier */
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mask = RK3399_CORECFG_CLOCKMULTIPLIER;
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val = 0;
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SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val);
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/* Set base clock frequency */
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mask = RK3399_CORECFG_BASECLKFREQ;
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val = SHIFTIN((freq + (1000000 / 2)) / 1000000,
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RK3399_CORECFG_BASECLKFREQ);
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SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val);
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return (0);
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}
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static uint8_t
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sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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return (bus_read_1(sc->mem_res[slot->num], off));
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}
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static void
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sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint8_t val)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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bus_write_1(sc->mem_res[slot->num], off, val);
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}
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static uint16_t
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sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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return (bus_read_2(sc->mem_res[slot->num], off));
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}
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static void
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sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint16_t val)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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bus_write_2(sc->mem_res[slot->num], off, val);
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}
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static uint32_t
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sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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uint32_t val32;
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val32 = bus_read_4(sc->mem_res[slot->num], off);
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if (off == SDHCI_CAPABILITIES && sc->no_18v)
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val32 &= ~SDHCI_CAN_VDD_180;
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return (val32);
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}
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static void
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sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint32_t val)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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bus_write_4(sc->mem_res[slot->num], off, val);
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}
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static void
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sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot,
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bus_size_t off, uint32_t *data, bus_size_t count)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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bus_read_multi_4(sc->mem_res[slot->num], off, data, count);
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}
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static void
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sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot,
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bus_size_t off, uint32_t *data, bus_size_t count)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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bus_write_multi_4(sc->mem_res[slot->num], off, data, count);
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}
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static void
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sdhci_fdt_intr(void *arg)
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{
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struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg;
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int i;
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for (i = 0; i < sc->num_slots; i++)
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sdhci_generic_intr(&sc->slots[i]);
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}
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static int
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sdhci_fdt_get_ro(device_t bus, device_t dev)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(bus);
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return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted);
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}
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static int
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sdhci_fdt_set_clock(device_t dev, struct sdhci_slot *slot, int clock)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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int32_t val;
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int i;
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data ==
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SDHCI_FDT_RK3568) {
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if (clock == 400000)
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clock = 375000;
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if (clock) {
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clk_set_freq(sc->clk_core, clock, 0);
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if (clock <= 52000000) {
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bus_write_4(sc->mem_res[slot->num],
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RK3568_EMMC_DLL_CTRL, 0x0);
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bus_write_4(sc->mem_res[slot->num],
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RK3568_EMMC_DLL_RXCLK, DLL_RXCLK_NO_INV);
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bus_write_4(sc->mem_res[slot->num],
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RK3568_EMMC_DLL_TXCLK, 0x0);
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bus_write_4(sc->mem_res[slot->num],
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RK3568_EMMC_DLL_STRBIN, 0x0);
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return (clock);
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}
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bus_write_4(sc->mem_res[slot->num],
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RK3568_EMMC_DLL_CTRL, DLL_CTRL_START);
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DELAY(1000);
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bus_write_4(sc->mem_res[slot->num],
|
|
RK3568_EMMC_DLL_CTRL, 0);
|
|
bus_write_4(sc->mem_res[slot->num],
|
|
RK3568_EMMC_DLL_CTRL, DLL_CTRL_START_POINT_DEFAULT |
|
|
DLL_CTRL_INCREMENT_DEFAULT | DLL_CTRL_START);
|
|
for (i = 0; i < 500; i++) {
|
|
val = bus_read_4(sc->mem_res[slot->num],
|
|
RK3568_EMMC_DLL_STATUS0);
|
|
if (val & DLL_STATUS0_DLL_LOCK &&
|
|
!(val & DLL_STATUS0_DLL_TIMEOUT))
|
|
break;
|
|
DELAY(1000);
|
|
}
|
|
bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_ATCTRL,
|
|
(0x1 << 16 | 0x2 << 17 | 0x3 << 19));
|
|
bus_write_4(sc->mem_res[slot->num],
|
|
RK3568_EMMC_DLL_RXCLK,
|
|
DLL_RXCLK_DELAY_ENABLE | DLL_RXCLK_NO_INV);
|
|
bus_write_4(sc->mem_res[slot->num],
|
|
RK3568_EMMC_DLL_TXCLK, DLL_TXCLK_DELAY_ENABLE |
|
|
DLL_TXCLK_TAPNUM_DEFAULT|DLL_TXCLK_TAPNUM_FROM_SW);
|
|
bus_write_4(sc->mem_res[slot->num],
|
|
RK3568_EMMC_DLL_STRBIN, DLL_STRBIN_DELAY_ENABLE |
|
|
DLL_STRBIN_TAPNUM_DEFAULT |
|
|
DLL_STRBIN_TAPNUM_FROM_SW);
|
|
}
|
|
}
|
|
return (clock);
|
|
}
|
|
|
|
static int
|
|
sdhci_fdt_probe(device_t dev)
|
|
{
|
|
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
|
phandle_t node;
|
|
pcell_t cid;
|
|
|
|
sc->quirks = 0;
|
|
sc->num_slots = 1;
|
|
sc->max_clk = 0;
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
|
|
case SDHCI_FDT_ARMADA38X:
|
|
sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP;
|
|
device_set_desc(dev, "ARMADA38X SDHCI controller");
|
|
break;
|
|
case SDHCI_FDT_GENERIC:
|
|
device_set_desc(dev, "generic fdt SDHCI controller");
|
|
break;
|
|
case SDHCI_FDT_QUALCOMM:
|
|
sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
|
|
SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY;
|
|
sc->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
|
|
device_set_desc(dev, "Qualcomm FDT SDHCI controller");
|
|
break;
|
|
case SDHCI_FDT_RK3399:
|
|
device_set_desc(dev, "Rockchip RK3399 fdt SDHCI controller");
|
|
break;
|
|
case SDHCI_FDT_XLNX_ZY7:
|
|
sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
|
|
device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller");
|
|
break;
|
|
case SDHCI_FDT_RK3568:
|
|
device_set_desc(dev, "Rockchip RK3568 fdt SDHCI controller");
|
|
break;
|
|
default:
|
|
return (ENXIO);
|
|
}
|
|
|
|
node = ofw_bus_get_node(dev);
|
|
|
|
/* Allow dts to patch quirks, slots, and max-frequency. */
|
|
if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0)
|
|
sc->quirks = cid;
|
|
if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0)
|
|
sc->num_slots = cid;
|
|
if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
|
|
sc->max_clk = cid;
|
|
if (OF_hasprop(node, "no-1-8-v"))
|
|
sc->no_18v = true;
|
|
if (OF_hasprop(node, "wp-inverted"))
|
|
sc->wp_inverted = true;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sdhci_fdt_attach(device_t dev)
|
|
{
|
|
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
|
struct sdhci_slot *slot;
|
|
int err, slots, rid, i;
|
|
|
|
sc->dev = dev;
|
|
|
|
/* Allocate IRQ. */
|
|
rid = 0;
|
|
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->irq_res == NULL) {
|
|
device_printf(dev, "Can't allocate IRQ\n");
|
|
return (ENOMEM);
|
|
}
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data ==
|
|
SDHCI_FDT_RK3399) {
|
|
/* Initialize SDHCI */
|
|
err = sdhci_init_rk3399(dev);
|
|
if (err != 0) {
|
|
device_printf(dev, "Cannot init RK3399 SDHCI\n");
|
|
return (err);
|
|
}
|
|
}
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data ==
|
|
SDHCI_FDT_RK3568) {
|
|
/* setup & enable clocks */
|
|
if (clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core)) {
|
|
device_printf(dev, "cannot get core clock\n");
|
|
return (ENXIO);
|
|
}
|
|
clk_enable(sc->clk_core);
|
|
}
|
|
|
|
/* Scan all slots. */
|
|
slots = sc->num_slots; /* number of slots determined in probe(). */
|
|
sc->num_slots = 0;
|
|
for (i = 0; i < slots; i++) {
|
|
slot = &sc->slots[sc->num_slots];
|
|
|
|
/* Allocate memory. */
|
|
rid = 0;
|
|
sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&rid, RF_ACTIVE);
|
|
if (sc->mem_res[i] == NULL) {
|
|
device_printf(dev,
|
|
"Can't allocate memory for slot %d\n", i);
|
|
continue;
|
|
}
|
|
|
|
slot->quirks = sc->quirks;
|
|
slot->caps = sc->caps;
|
|
slot->max_clk = sc->max_clk;
|
|
slot->sdma_boundary = sc->sdma_boundary;
|
|
|
|
if (sdhci_init_slot(dev, slot, i) != 0)
|
|
continue;
|
|
|
|
sc->num_slots++;
|
|
}
|
|
device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
|
|
|
|
/* Activate the interrupt */
|
|
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
|
NULL, sdhci_fdt_intr, sc, &sc->intrhand);
|
|
if (err) {
|
|
device_printf(dev, "Cannot setup IRQ\n");
|
|
return (err);
|
|
}
|
|
|
|
/* Process cards detection. */
|
|
for (i = 0; i < sc->num_slots; i++)
|
|
sdhci_start_slot(&sc->slots[i]);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sdhci_fdt_detach(device_t dev)
|
|
{
|
|
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
|
int i;
|
|
|
|
bus_generic_detach(dev);
|
|
bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
|
|
bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
|
|
sc->irq_res);
|
|
|
|
for (i = 0; i < sc->num_slots; i++) {
|
|
sdhci_cleanup_slot(&sc->slots[i]);
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t sdhci_fdt_methods[] = {
|
|
/* device_if */
|
|
DEVMETHOD(device_probe, sdhci_fdt_probe),
|
|
DEVMETHOD(device_attach, sdhci_fdt_attach),
|
|
DEVMETHOD(device_detach, sdhci_fdt_detach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
|
|
|
|
/* mmcbr_if */
|
|
DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
|
|
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
|
DEVMETHOD(mmcbr_get_ro, sdhci_fdt_get_ro),
|
|
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
|
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
|
|
|
/* SDHCI registers accessors */
|
|
DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1),
|
|
DEVMETHOD(sdhci_read_2, sdhci_fdt_read_2),
|
|
DEVMETHOD(sdhci_read_4, sdhci_fdt_read_4),
|
|
DEVMETHOD(sdhci_read_multi_4, sdhci_fdt_read_multi_4),
|
|
DEVMETHOD(sdhci_write_1, sdhci_fdt_write_1),
|
|
DEVMETHOD(sdhci_write_2, sdhci_fdt_write_2),
|
|
DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4),
|
|
DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4),
|
|
DEVMETHOD(sdhci_set_clock, sdhci_fdt_set_clock),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t sdhci_fdt_driver = {
|
|
"sdhci_fdt",
|
|
sdhci_fdt_methods,
|
|
sizeof(struct sdhci_fdt_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, NULL, NULL);
|
|
SDHCI_DEPEND(sdhci_fdt);
|
|
#ifndef MMCCAM
|
|
MMC_DECLARE_BRIDGE(sdhci_fdt);
|
|
#endif
|