It includes: 1)Newly added TMF feature. 2)Added newly Huawei & Inspur PCI ID's 3)Fixed smartpqi driver hangs in Z-Pool while running on FreeBSD12.1 4)Fixed flooding dmesg in kernel while the controller is offline during in ioctls. 5)Avoided unnecessary host memory allocation for rcb sg buffers. 6)Fixed race conditions while accessing internal rcb structure. 7)Fixed where Logical volumes exposing two different names to the OS it's due to the system memory is overwritten with DMA stale data. 8)Fixed dynamically unloading a smartpqi driver. 9)Added device_shutdown callback instead of deprecated shutdown_final kernel event in smartpqi driver. 10)Fixed where Os is crashed during physical drive hot removal during heavy IO. 11)Fixed OS crash during controller lockup/offline during heavy IO. 12)Fixed coverity issues in smartpqi driver 13)Fixed system crash while creating and deleting logical volume in a continuous loop. 14)Fixed where the volume size is not exposing to OS when it expands. 15)Added HC3 pci id's. Reviewed by: Scott Benesh (microsemi), Murthy Bhat (microsemi), imp Differential Revision: https://reviews.freebsd.org/D30182 Sponsored by: Netflix
514 lines
13 KiB
C
514 lines
13 KiB
C
/*-
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* Copyright 2016-2021 Microchip Technology, Inc. and/or its subsidiaries.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#include "smartpqi_includes.h"
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/* Function for disabling msix interrupots */
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void
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sis_disable_msix(pqisrc_softstate_t *softs)
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{
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uint32_t db_reg;
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DBG_FUNC("IN\n");
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db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR);
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db_reg &= ~SIS_ENABLE_MSIX;
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PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR, db_reg);
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DBG_FUNC("OUT\n");
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}
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void
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sis_enable_intx(pqisrc_softstate_t *softs)
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{
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uint32_t db_reg;
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DBG_FUNC("IN\n");
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db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR);
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db_reg |= SIS_ENABLE_INTX;
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PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR, db_reg);
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if (pqisrc_sis_wait_for_db_bit_to_clear(softs,SIS_ENABLE_INTX)
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!= PQI_STATUS_SUCCESS) {
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DBG_ERR("Failed to wait for enable intx db bit to clear\n");
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}
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DBG_FUNC("OUT\n");
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}
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void
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sis_disable_intx(pqisrc_softstate_t *softs)
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{
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uint32_t db_reg;
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DBG_FUNC("IN\n");
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db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR);
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db_reg &= ~SIS_ENABLE_INTX;
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PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR, db_reg);
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DBG_FUNC("OUT\n");
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}
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void
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sis_disable_interrupt(pqisrc_softstate_t *softs)
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{
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DBG_FUNC("IN");
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switch(softs->intr_type) {
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case INTR_TYPE_FIXED:
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pqisrc_configure_legacy_intx(softs,false);
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sis_disable_intx(softs);
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break;
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case INTR_TYPE_MSI:
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case INTR_TYPE_MSIX:
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sis_disable_msix(softs);
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break;
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default:
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DBG_ERR("Inerrupt mode none!\n");
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break;
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}
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DBG_FUNC("OUT");
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}
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/* Trigger a NMI as part of taking controller offline procedure */
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void
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pqisrc_trigger_nmi_sis(pqisrc_softstate_t *softs)
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{
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DBG_FUNC("IN\n");
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PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR, LE_32(TRIGGER_NMI_SIS));
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DBG_FUNC("OUT\n");
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}
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/* Switch the adapter back to SIS mode during uninitialization */
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int
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pqisrc_reenable_sis(pqisrc_softstate_t *softs)
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{
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int ret = PQI_STATUS_SUCCESS;
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uint32_t timeout = SIS_ENABLE_TIMEOUT;
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DBG_FUNC("IN\n");
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PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR, LE_32(REENABLE_SIS));
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COND_WAIT(((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &
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REENABLE_SIS) == 0), timeout)
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if (!timeout) {
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DBG_WARN(" [ %s ] failed to re enable sis\n",__func__);
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ret = PQI_STATUS_TIMEOUT;
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}
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DBG_FUNC("OUT\n");
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return ret;
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}
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/* Validate the FW status PQI_CTRL_KERNEL_UP_AND_RUNNING */
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int
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pqisrc_check_fw_status(pqisrc_softstate_t *softs)
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{
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int ret = PQI_STATUS_SUCCESS;
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uint32_t timeout = SIS_STATUS_OK_TIMEOUT;
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DBG_FUNC("IN\n");
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OS_SLEEP(1000000);
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COND_WAIT((GET_FW_STATUS(softs) &
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PQI_CTRL_KERNEL_UP_AND_RUNNING), timeout);
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if (!timeout) {
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DBG_ERR("FW check status timedout\n");
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ret = PQI_STATUS_TIMEOUT;
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}
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DBG_FUNC("OUT\n");
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return ret;
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}
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/* Function used to submit a SIS command to the adapter */
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static int
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pqisrc_send_sis_cmd(pqisrc_softstate_t *softs, uint32_t *mb)
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{
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int ret = PQI_STATUS_SUCCESS;
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int i = 0;
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uint32_t timeout = SIS_CMD_COMPLETE_TIMEOUT;
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int val;
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DBG_FUNC("IN\n");
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/* Copy Command to mailbox */
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for (i = 0; i < 6; i++)
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PCI_MEM_PUT32(softs, &softs->ioa_reg->mb[i],
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LEGACY_SIS_SRCV_MAILBOX+i*4, LE_32(mb[i]));
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/* TODO : Switch to INTX Mode ?*/
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PCI_MEM_PUT32(softs, &softs->ioa_reg->ioa_to_host_db_clr,
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LEGACY_SIS_ODBR_R, LE_32(0x1000));
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/* Submit the command */
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PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR, LE_32(SIS_CMD_SUBMIT));
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#ifdef SIS_POLL_WAIT
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/* Wait for 20 milli sec to poll */
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OS_BUSYWAIT(SIS_POLL_START_WAIT_TIME);
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#endif
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val = PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R);
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DBG_FUNC("val : %x\n",val);
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/* Spin waiting for the command to complete */
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COND_WAIT((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &
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SIS_CMD_COMPLETE), timeout);
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if (!timeout) {
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DBG_ERR("Sync command %x, timedout\n", mb[0]);
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ret = PQI_STATUS_TIMEOUT;
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goto err_out;
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}
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/* Check command status */
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mb[0] = LE_32(PCI_MEM_GET32(softs, &softs->ioa_reg->mb[0], LEGACY_SIS_SRCV_MAILBOX));
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if (mb[0] != SIS_CMD_STATUS_SUCCESS) {
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DBG_ERR("SIS cmd failed with status = 0x%x\n",
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mb[0]);
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ret = PQI_STATUS_FAILURE;
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goto err_out;
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}
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/* Copy the mailbox back */
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for (i = 1; i < 6; i++)
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mb[i] = LE_32(PCI_MEM_GET32(softs, &softs->ioa_reg->mb[i], LEGACY_SIS_SRCV_MAILBOX+i*4));
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DBG_FUNC("OUT\n");
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return ret;
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err_out:
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DBG_FUNC("OUT failed\n");
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return ret;
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}
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/* First SIS command for the adapter to check PQI support */
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int
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pqisrc_get_adapter_properties(pqisrc_softstate_t *softs,
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uint32_t *prop, uint32_t *ext_prop)
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{
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int ret = PQI_STATUS_SUCCESS;
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uint32_t mb[6] = {0};
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DBG_FUNC("IN\n");
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mb[0] = SIS_CMD_GET_ADAPTER_PROPERTIES;
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ret = pqisrc_send_sis_cmd(softs, mb);
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if (!ret) {
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DBG_INIT("GET_PROPERTIES prop = %x, ext_prop = %x\n",
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mb[1], mb[4]);
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*prop = mb[1];
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*ext_prop = mb[4];
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}
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DBG_FUNC("OUT\n");
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return ret;
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}
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/* Second SIS command to the adapter GET_COMM_PREFERRED_SETTINGS */
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int
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pqisrc_get_preferred_settings(pqisrc_softstate_t *softs)
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{
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int ret = PQI_STATUS_SUCCESS;
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uint32_t mb[6] = {0};
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DBG_FUNC("IN\n");
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mb[0] = SIS_CMD_GET_COMM_PREFERRED_SETTINGS;
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ret = pqisrc_send_sis_cmd(softs, mb);
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if (!ret) {
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/* 31:16 maximum command size in KB */
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softs->pref_settings.max_cmd_size = mb[1] >> 16;
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/* 15:00: Maximum FIB size in bytes */
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softs->pref_settings.max_fib_size = mb[1] & 0x0000FFFF;
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DBG_INIT("cmd size = %x, fib size = %x\n",
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softs->pref_settings.max_cmd_size,
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softs->pref_settings.max_fib_size);
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}
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DBG_FUNC("OUT\n");
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return ret;
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}
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/* Get supported PQI capabilities from the adapter */
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int
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pqisrc_get_sis_pqi_cap(pqisrc_softstate_t *softs)
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{
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int ret = PQI_STATUS_SUCCESS;
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uint32_t mb[6] = {0};
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DBG_FUNC("IN\n");
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mb[0] = SIS_CMD_GET_PQI_CAPABILITIES;
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ret = pqisrc_send_sis_cmd(softs, mb);
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if (!ret) {
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softs->pqi_cap.max_sg_elem = mb[1];
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softs->pqi_cap.max_transfer_size = mb[2];
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softs->pqi_cap.max_outstanding_io = mb[3];
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softs->pqi_cap.conf_tab_off = mb[4];
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softs->pqi_cap.conf_tab_sz = mb[5];
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os_update_dma_attributes(softs);
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DBG_INIT("max_sg_elem = %x\n",
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softs->pqi_cap.max_sg_elem);
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DBG_INIT("max_transfer_size = %x\n",
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softs->pqi_cap.max_transfer_size);
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DBG_INIT("max_outstanding_io = %x\n",
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softs->pqi_cap.max_outstanding_io);
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}
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DBG_FUNC("OUT\n");
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return ret;
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}
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/* Send INIT STRUCT BASE ADDR - one of the SIS command */
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int
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pqisrc_init_struct_base(pqisrc_softstate_t *softs)
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{
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int ret = PQI_STATUS_SUCCESS;
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uint32_t elem_size = 0;
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uint32_t num_elem = 0;
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struct dma_mem init_struct_mem = {0};
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struct init_base_struct *init_struct = NULL;
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uint32_t mb[6] = {0};
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DBG_FUNC("IN\n");
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/* Allocate init struct */
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memset(&init_struct_mem, 0, sizeof(struct dma_mem));
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init_struct_mem.size = sizeof(struct init_base_struct);
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init_struct_mem.align = PQISRC_INIT_STRUCT_DMA_ALIGN;
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init_struct_mem.tag = "init_struct";
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ret = os_dma_mem_alloc(softs, &init_struct_mem);
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if (ret) {
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DBG_ERR("Failed to Allocate error buffer ret : %d\n",
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ret);
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goto err_out;
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}
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/* Calculate error buffer size */
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/* The valid tag values are from 1, 2, ..., softs->max_outstanding_io
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* The rcb and error buffer will be accessed by using the tag as index
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* As 0 tag index is not used, we need to allocate one extra.
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*/
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num_elem = softs->pqi_cap.max_outstanding_io + 1;
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elem_size = PQISRC_ERR_BUF_ELEM_SIZE;
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softs->err_buf_dma_mem.size = num_elem * elem_size;
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/* Allocate error buffer */
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softs->err_buf_dma_mem.align = PQISRC_ERR_BUF_DMA_ALIGN;
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softs->err_buf_dma_mem.tag = "error_buffer";
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ret = os_dma_mem_alloc(softs, &softs->err_buf_dma_mem);
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if (ret) {
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DBG_ERR("Failed to Allocate error buffer ret : %d\n",
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ret);
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goto err_error_buf_alloc;
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}
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/* Fill init struct */
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init_struct = (struct init_base_struct *)DMA_TO_VIRT(&init_struct_mem);
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init_struct->revision = PQISRC_INIT_STRUCT_REVISION;
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init_struct->flags = 0;
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init_struct->err_buf_paddr_l = DMA_PHYS_LOW(&softs->err_buf_dma_mem);
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init_struct->err_buf_paddr_h = DMA_PHYS_HIGH(&softs->err_buf_dma_mem);
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init_struct->err_buf_elem_len = elem_size;
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init_struct->err_buf_num_elem = num_elem;
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mb[0] = SIS_CMD_INIT_BASE_STRUCT_ADDRESS;
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mb[1] = DMA_PHYS_LOW(&init_struct_mem);
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mb[2] = DMA_PHYS_HIGH(&init_struct_mem);
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mb[3] = init_struct_mem.size;
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ret = pqisrc_send_sis_cmd(softs, mb);
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if (ret)
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goto err_sis_cmd;
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DBG_FUNC("OUT\n");
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os_dma_mem_free(softs, &init_struct_mem);
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return ret;
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err_sis_cmd:
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os_dma_mem_free(softs, &softs->err_buf_dma_mem);
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err_error_buf_alloc:
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os_dma_mem_free(softs, &init_struct_mem);
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err_out:
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DBG_FUNC("OUT failed %d\n", ret);
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return PQI_STATUS_FAILURE;
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}
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/*
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* SIS initialization of the adapter in a sequence of
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* - GET_ADAPTER_PROPERTIES
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* - GET_COMM_PREFERRED_SETTINGS
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* - GET_PQI_CAPABILITIES
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* - INIT_STRUCT_BASE ADDR
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*/
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int
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pqisrc_sis_init(pqisrc_softstate_t *softs)
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{
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int ret = PQI_STATUS_SUCCESS;
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uint32_t prop = 0;
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uint32_t ext_prop = 0;
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DBG_FUNC("IN\n");
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ret = pqisrc_force_sis(softs);
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if (ret) {
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DBG_ERR("Failed to switch back the adapter to SIS mode!\n");
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goto err_out;
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}
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/* Check FW status ready */
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ret = pqisrc_check_fw_status(softs);
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if (ret) {
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DBG_ERR("PQI Controller is not ready !!!\n");
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goto err_out;
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}
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/* Check For PQI support(19h) */
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ret = pqisrc_get_adapter_properties(softs, &prop, &ext_prop);
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if (ret) {
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DBG_ERR("Failed to get adapter properties\n");
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goto err_out;
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}
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if (!((prop & SIS_SUPPORT_EXT_OPT) &&
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(ext_prop & SIS_SUPPORT_PQI))) {
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DBG_ERR("PQI Mode Not Supported\n");
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ret = PQI_STATUS_FAILURE;
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goto err_out;
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}
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softs->pqi_reset_quiesce_allowed = false;
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if (ext_prop & SIS_SUPPORT_PQI_RESET_QUIESCE)
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softs->pqi_reset_quiesce_allowed = true;
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/* Send GET_COMM_PREFERRED_SETTINGS (26h) */
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ret = pqisrc_get_preferred_settings(softs);
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if (ret) {
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DBG_ERR("Failed to get adapter pref settings\n");
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goto err_out;
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}
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/* Get PQI settings , 3000h*/
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ret = pqisrc_get_sis_pqi_cap(softs);
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if (ret) {
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DBG_ERR("Failed to get PQI Capabilities\n");
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goto err_out;
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}
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/* We need to allocate DMA memory here ,
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* Do any os specific DMA setup.
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*/
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ret = os_dma_setup(softs);
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if (ret) {
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DBG_ERR("Failed to Setup DMA\n");
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goto err_out;
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}
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/* Init struct base addr */
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ret = pqisrc_init_struct_base(softs);
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if (ret) {
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DBG_ERR("Failed to set init struct base addr\n");
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goto err_dma;
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}
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DBG_FUNC("OUT\n");
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return ret;
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err_dma:
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os_dma_destroy(softs);
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err_out:
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DBG_FUNC("OUT failed\n");
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return ret;
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}
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/* Deallocate the resources used during SIS initialization */
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void
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pqisrc_sis_uninit(pqisrc_softstate_t *softs)
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{
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DBG_FUNC("IN\n");
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|
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os_dma_mem_free(softs, &softs->err_buf_dma_mem);
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os_dma_destroy(softs);
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os_resource_free(softs);
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pqi_reset(softs);
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|
|
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DBG_FUNC("OUT\n");
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}
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|
|
int
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|
pqisrc_sis_wait_for_db_bit_to_clear(pqisrc_softstate_t *softs, uint32_t bit)
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|
{
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|
int rcode = PQI_STATUS_SUCCESS;
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uint32_t db_reg;
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uint32_t loop_cnt = 0;
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|
|
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DBG_FUNC("IN\n");
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|
|
|
while (1) {
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db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
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LEGACY_SIS_IDBR);
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if ((db_reg & bit) == 0)
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|
break;
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|
if (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_PANIC) {
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|
DBG_ERR("controller kernel panic\n");
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|
rcode = PQI_STATUS_FAILURE;
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|
break;
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|
}
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|
if (loop_cnt++ == SIS_DB_BIT_CLEAR_TIMEOUT_CNT) {
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|
DBG_ERR("door-bell reg bit 0x%x not cleared\n", bit);
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|
rcode = PQI_STATUS_TIMEOUT;
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|
break;
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|
}
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|
OS_SLEEP(500);
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|
}
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|
|
|
DBG_FUNC("OUT\n");
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|
|
|
return rcode;
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|
}
|