Rename pci_host_generic_attach to pci_host_generic_fdt_attach to be consistant with the acpi attachment. Sponsored by: The FreeBSD Foundation
790 lines
18 KiB
C
790 lines
18 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/types.h>
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#include <sys/sysctl.h>
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#include <sys/kernel.h>
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#include <sys/rman.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/cpuset.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_kern.h>
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#include <vm/pmap.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pci_host_generic.h>
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#include <dev/pci/pci_host_generic_fdt.h>
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#include <dev/pci/pcib_private.h>
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#include "xlnx_pcib.h"
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#include "ofw_bus_if.h"
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#include "msi_if.h"
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#include "pcib_if.h"
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#include "pic_if.h"
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#define XLNX_PCIB_MAX_MSI 64
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static int xlnx_pcib_fdt_attach(device_t);
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static int xlnx_pcib_fdt_probe(device_t);
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static int xlnx_pcib_fdt_get_id(device_t, device_t, enum pci_id_type,
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uintptr_t *);
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static void xlnx_pcib_msi_mask(device_t dev, struct intr_irqsrc *isrc,
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bool mask);
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struct xlnx_pcib_softc {
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struct generic_pcie_fdt_softc fdt_sc;
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struct resource *res[4];
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struct mtx mtx;
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vm_offset_t msi_page;
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struct xlnx_pcib_irqsrc *isrcs;
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device_t dev;
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void *intr_cookie[3];
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};
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static struct resource_spec xlnx_pcib_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 2, RF_ACTIVE },
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{ -1, 0 }
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};
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struct xlnx_pcib_irqsrc {
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struct intr_irqsrc isrc;
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u_int irq;
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#define XLNX_IRQ_FLAG_USED (1 << 0)
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u_int flags;
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};
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static void
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xlnx_pcib_clear_err_interrupts(struct generic_pcie_core_softc *sc)
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{
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uint32_t reg;
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reg = bus_read_4(sc->res, XLNX_PCIE_RPERRFRR);
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if (reg & RPERRFRR_VALID) {
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device_printf(sc->dev, "Requested ID: %x\n",
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reg & RPERRFRR_REQ_ID_M);
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bus_write_4(sc->res, XLNX_PCIE_RPERRFRR, ~0U);
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}
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}
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static int
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xlnx_pcib_intr(void *arg)
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{
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struct generic_pcie_fdt_softc *fdt_sc;
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struct generic_pcie_core_softc *sc;
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struct xlnx_pcib_softc *xlnx_sc;
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uint32_t val, mask, status;
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xlnx_sc = arg;
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fdt_sc = &xlnx_sc->fdt_sc;
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sc = &fdt_sc->base;
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val = bus_read_4(sc->res, XLNX_PCIE_IDR);
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mask = bus_read_4(sc->res, XLNX_PCIE_IMR);
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status = val & mask;
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if (!status)
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return (FILTER_HANDLED);
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if (status & IMR_LINK_DOWN)
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device_printf(sc->dev, "Link down");
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if (status & IMR_HOT_RESET)
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device_printf(sc->dev, "Hot reset");
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if (status & IMR_CORRECTABLE)
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xlnx_pcib_clear_err_interrupts(sc);
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if (status & IMR_FATAL)
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xlnx_pcib_clear_err_interrupts(sc);
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if (status & IMR_NON_FATAL)
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xlnx_pcib_clear_err_interrupts(sc);
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if (status & IMR_MSI) {
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device_printf(sc->dev, "MSI interrupt");
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/* FIFO mode MSI not implemented. */
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}
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if (status & IMR_INTX) {
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device_printf(sc->dev, "INTx received");
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/* Not implemented. */
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}
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if (status & IMR_SLAVE_UNSUPP_REQ)
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device_printf(sc->dev, "Slave unsupported request");
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if (status & IMR_SLAVE_UNEXP_COMPL)
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device_printf(sc->dev, "Slave unexpected completion");
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if (status & IMR_SLAVE_COMPL_TIMOUT)
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device_printf(sc->dev, "Slave completion timeout");
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if (status & IMR_SLAVE_ERROR_POISON)
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device_printf(sc->dev, "Slave error poison");
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if (status & IMR_SLAVE_COMPL_ABORT)
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device_printf(sc->dev, "Slave completion abort");
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if (status & IMR_SLAVE_ILLEG_BURST)
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device_printf(sc->dev, "Slave illegal burst");
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if (status & IMR_MASTER_DECERR)
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device_printf(sc->dev, "Master decode error");
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if (status & IMR_MASTER_SLVERR)
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device_printf(sc->dev, "Master slave error");
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bus_write_4(sc->res, XLNX_PCIE_IDR, val);
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return (FILTER_HANDLED);
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}
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static void
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xlnx_pcib_handle_msi_intr(void *arg, int msireg)
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{
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struct generic_pcie_fdt_softc *fdt_sc;
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struct generic_pcie_core_softc *sc;
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struct xlnx_pcib_softc *xlnx_sc;
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struct xlnx_pcib_irqsrc *xi;
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struct trapframe *tf;
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int irq;
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int reg;
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int i;
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xlnx_sc = arg;
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fdt_sc = &xlnx_sc->fdt_sc;
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sc = &fdt_sc->base;
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tf = curthread->td_intr_frame;
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do {
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reg = bus_read_4(sc->res, msireg);
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for (i = 0; i < sizeof(uint32_t) * 8; i++) {
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if (reg & (1 << i)) {
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bus_write_4(sc->res, msireg, (1 << i));
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irq = i;
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if (msireg == XLNX_PCIE_RPMSIID2)
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irq += 32;
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xi = &xlnx_sc->isrcs[irq];
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if (intr_isrc_dispatch(&xi->isrc, tf) != 0) {
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/* Disable stray. */
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xlnx_pcib_msi_mask(sc->dev,
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&xi->isrc, 1);
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device_printf(sc->dev,
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"Stray irq %u disabled\n", irq);
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}
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}
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}
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} while (reg != 0);
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}
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static int
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xlnx_pcib_msi0_intr(void *arg)
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{
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xlnx_pcib_handle_msi_intr(arg, XLNX_PCIE_RPMSIID1);
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return (FILTER_HANDLED);
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}
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static int
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xlnx_pcib_msi1_intr(void *arg)
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{
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xlnx_pcib_handle_msi_intr(arg, XLNX_PCIE_RPMSIID2);
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return (FILTER_HANDLED);
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}
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static int
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xlnx_pcib_register_msi(struct xlnx_pcib_softc *sc)
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{
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const char *name;
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int error;
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int irq;
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sc->isrcs = malloc(sizeof(*sc->isrcs) * XLNX_PCIB_MAX_MSI, M_DEVBUF,
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M_WAITOK | M_ZERO);
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name = device_get_nameunit(sc->dev);
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for (irq = 0; irq < XLNX_PCIB_MAX_MSI; irq++) {
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sc->isrcs[irq].irq = irq;
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error = intr_isrc_register(&sc->isrcs[irq].isrc,
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sc->dev, 0, "%s,%u", name, irq);
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if (error != 0)
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return (error); /* XXX deregister ISRCs */
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}
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if (intr_msi_register(sc->dev,
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OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0)
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return (ENXIO);
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return (0);
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}
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static void
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xlnx_pcib_init(struct xlnx_pcib_softc *sc)
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{
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bus_addr_t addr;
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int reg;
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/* Disable interrupts. */
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bus_write_4(sc->res[0], XLNX_PCIE_IMR, 0);
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/* Clear pending interrupts.*/
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reg = bus_read_4(sc->res[0], XLNX_PCIE_IDR);
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bus_write_4(sc->res[0], XLNX_PCIE_IDR, reg);
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/* Setup an MSI page. */
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sc->msi_page = kmem_alloc_contig(PAGE_SIZE, M_WAITOK, 0,
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BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
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addr = vtophys(sc->msi_page);
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bus_write_4(sc->res[0], XLNX_PCIE_RPMSIBR1, (addr >> 32));
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bus_write_4(sc->res[0], XLNX_PCIE_RPMSIBR2, (addr >> 0));
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/* Enable the bridge. */
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reg = bus_read_4(sc->res[0], XLNX_PCIE_RPSCR);
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reg |= RPSCR_BE;
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bus_write_4(sc->res[0], XLNX_PCIE_RPSCR, reg);
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/* Enable interrupts. */
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reg = IMR_LINK_DOWN
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| IMR_HOT_RESET
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| IMR_CFG_COMPL_STATUS_M
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| IMR_CFG_TIMEOUT
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| IMR_CORRECTABLE
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| IMR_NON_FATAL
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| IMR_FATAL
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| IMR_INTX
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| IMR_MSI
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| IMR_SLAVE_UNSUPP_REQ
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| IMR_SLAVE_UNEXP_COMPL
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| IMR_SLAVE_COMPL_TIMOUT
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| IMR_SLAVE_ERROR_POISON
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| IMR_SLAVE_COMPL_ABORT
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| IMR_SLAVE_ILLEG_BURST
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| IMR_MASTER_DECERR
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| IMR_MASTER_SLVERR;
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bus_write_4(sc->res[0], XLNX_PCIE_IMR, reg);
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}
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static int
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xlnx_pcib_fdt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "xlnx,xdma-host-3.00")) {
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device_set_desc(dev, "Xilinx XDMA PCIe Controller");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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xlnx_pcib_fdt_attach(device_t dev)
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{
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struct xlnx_pcib_softc *sc;
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int error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF);
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if (bus_alloc_resources(dev, xlnx_pcib_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Setup MISC interrupt handler. */
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error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
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xlnx_pcib_intr, NULL, sc, &sc->intr_cookie[0]);
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if (error != 0) {
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device_printf(dev, "could not setup interrupt handler.\n");
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return (ENXIO);
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}
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/* Setup MSI0 interrupt handler. */
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error = bus_setup_intr(dev, sc->res[2], INTR_TYPE_MISC | INTR_MPSAFE,
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xlnx_pcib_msi0_intr, NULL, sc, &sc->intr_cookie[1]);
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if (error != 0) {
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device_printf(dev, "could not setup interrupt handler.\n");
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return (ENXIO);
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}
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/* Setup MSI1 interrupt handler. */
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error = bus_setup_intr(dev, sc->res[3], INTR_TYPE_MISC | INTR_MPSAFE,
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xlnx_pcib_msi1_intr, NULL, sc, &sc->intr_cookie[2]);
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if (error != 0) {
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device_printf(dev, "could not setup interrupt handler.\n");
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return (ENXIO);
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}
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xlnx_pcib_init(sc);
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/*
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* Allow the core driver to map registers.
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* We will be accessing the device memory using core_softc.
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*/
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bus_release_resources(dev, xlnx_pcib_spec, sc->res);
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error = xlnx_pcib_register_msi(sc);
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if (error)
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return (error);
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return (pci_host_generic_fdt_attach(dev));
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}
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static int
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xlnx_pcib_fdt_get_id(device_t pci, device_t child, enum pci_id_type type,
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uintptr_t *id)
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{
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phandle_t node;
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int bsf;
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if (type != PCI_ID_MSI)
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return (pcib_get_id(pci, child, type, id));
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node = ofw_bus_get_node(pci);
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if (OF_hasprop(node, "msi-map"))
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return (generic_pcie_get_id(pci, child, type, id));
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bsf = pci_get_rid(child);
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*id = (pci_get_domain(child) << PCI_RID_DOMAIN_SHIFT) | bsf;
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return (0);
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}
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static int
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xlnx_pcib_req_valid(struct generic_pcie_core_softc *sc,
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u_int bus, u_int slot, u_int func, u_int reg)
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{
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bus_space_handle_t h;
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bus_space_tag_t t;
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uint32_t val;
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t = sc->bst;
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h = sc->bsh;
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if ((bus < sc->bus_start) || (bus > sc->bus_end))
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return (0);
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if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
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(reg > PCIE_REGMAX))
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return (0);
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if (bus == 0 && slot > 0)
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return (0);
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val = bus_space_read_4(t, h, XLNX_PCIE_PHYSCR);
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if ((val & PHYSCR_LINK_UP) == 0) {
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/* Link is down */
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return (0);
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}
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/* Valid */
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return (1);
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}
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static uint32_t
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xlnx_pcib_read_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, int bytes)
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{
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struct generic_pcie_fdt_softc *fdt_sc;
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struct xlnx_pcib_softc *xlnx_sc;
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struct generic_pcie_core_softc *sc;
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bus_space_handle_t h;
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bus_space_tag_t t;
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uint64_t offset;
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uint32_t data;
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xlnx_sc = device_get_softc(dev);
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fdt_sc = &xlnx_sc->fdt_sc;
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sc = &fdt_sc->base;
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if (!xlnx_pcib_req_valid(sc, bus, slot, func, reg))
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return (~0U);
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offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
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t = sc->bst;
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h = sc->bsh;
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data = bus_space_read_4(t, h, offset & ~3);
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switch (bytes) {
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case 1:
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data >>= (offset & 3) * 8;
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data &= 0xff;
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break;
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case 2:
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data >>= (offset & 3) * 8;
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data = le16toh(data);
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break;
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case 4:
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data = le32toh(data);
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break;
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default:
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return (~0U);
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}
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return (data);
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}
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static void
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xlnx_pcib_write_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, uint32_t val, int bytes)
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{
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struct generic_pcie_fdt_softc *fdt_sc;
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struct xlnx_pcib_softc *xlnx_sc;
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struct generic_pcie_core_softc *sc;
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bus_space_handle_t h;
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bus_space_tag_t t;
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uint64_t offset;
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uint32_t data;
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xlnx_sc = device_get_softc(dev);
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fdt_sc = &xlnx_sc->fdt_sc;
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sc = &fdt_sc->base;
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if (!xlnx_pcib_req_valid(sc, bus, slot, func, reg))
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return;
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offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
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t = sc->bst;
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h = sc->bsh;
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/*
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* 32-bit access used due to a bug in the Xilinx bridge that
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* requires to write primary and secondary buses in one blast.
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*
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* TODO: This is probably wrong on big-endian.
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*/
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switch (bytes) {
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case 1:
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data = bus_space_read_4(t, h, offset & ~3);
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data &= ~(0xff << ((offset & 3) * 8));
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data |= (val & 0xff) << ((offset & 3) * 8);
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bus_space_write_4(t, h, offset & ~3, htole32(data));
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break;
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case 2:
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data = bus_space_read_4(t, h, offset & ~3);
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data &= ~(0xffff << ((offset & 3) * 8));
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data |= (val & 0xffff) << ((offset & 3) * 8);
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bus_space_write_4(t, h, offset & ~3, htole32(data));
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break;
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case 4:
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bus_space_write_4(t, h, offset, htole32(val));
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break;
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default:
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return;
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}
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}
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static int
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xlnx_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount,
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int *irqs)
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{
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phandle_t msi_parent;
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ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
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NULL);
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msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
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return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
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irqs));
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}
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static int
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xlnx_pcib_release_msi(device_t pci, device_t child, int count, int *irqs)
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{
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phandle_t msi_parent;
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ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
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NULL);
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msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
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return (intr_release_msi(pci, child, msi_parent, count, irqs));
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}
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static int
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xlnx_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
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uint32_t *data)
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{
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phandle_t msi_parent;
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ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
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NULL);
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msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
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return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
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}
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static int
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xlnx_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount,
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device_t *pic, struct intr_irqsrc **srcs)
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{
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struct xlnx_pcib_softc *sc;
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int irq, end_irq, i;
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bool found;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mtx);
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found = false;
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for (irq = 0; (irq + count - 1) < XLNX_PCIB_MAX_MSI; irq++) {
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/* Assume the range is valid. */
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found = true;
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/* Check this range is valid. */
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for (end_irq = irq; end_irq < irq + count; end_irq++) {
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if (sc->isrcs[end_irq].flags & XLNX_IRQ_FLAG_USED) {
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/* This is already used. */
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found = false;
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break;
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}
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}
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if (found)
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break;
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}
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if (!found || irq == (XLNX_PCIB_MAX_MSI - 1)) {
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/* Not enough interrupts were found. */
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mtx_unlock(&sc->mtx);
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return (ENXIO);
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}
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/* Mark the interrupt as used. */
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for (i = 0; i < count; i++)
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sc->isrcs[irq + i].flags |= XLNX_IRQ_FLAG_USED;
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mtx_unlock(&sc->mtx);
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for (i = 0; i < count; i++)
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srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i];
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*pic = device_get_parent(dev);
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return (0);
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}
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static int
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xlnx_pcib_msi_release_msi(device_t dev, device_t child, int count,
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struct intr_irqsrc **isrc)
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{
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struct xlnx_pcib_softc *sc;
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struct xlnx_pcib_irqsrc *xi;
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int i;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mtx);
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for (i = 0; i < count; i++) {
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xi = (struct xlnx_pcib_irqsrc *)isrc[i];
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KASSERT(xi->flags & XLNX_IRQ_FLAG_USED,
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("%s: Releasing an unused MSI interrupt", __func__));
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xi->flags &= ~XLNX_IRQ_FLAG_USED;
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}
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mtx_unlock(&sc->mtx);
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return (0);
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}
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static int
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xlnx_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
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uint64_t *addr, uint32_t *data)
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{
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struct xlnx_pcib_softc *sc;
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struct xlnx_pcib_irqsrc *xi;
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sc = device_get_softc(dev);
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xi = (struct xlnx_pcib_irqsrc *)isrc;
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*addr = vtophys(sc->msi_page);
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*data = xi->irq;
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return (0);
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}
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static void
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xlnx_pcib_msi_mask(device_t dev, struct intr_irqsrc *isrc, bool mask)
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{
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struct generic_pcie_fdt_softc *fdt_sc;
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struct generic_pcie_core_softc *sc;
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struct xlnx_pcib_softc *xlnx_sc;
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struct xlnx_pcib_irqsrc *xi;
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uint32_t msireg, irq;
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uint32_t reg;
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xlnx_sc = device_get_softc(dev);
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fdt_sc = &xlnx_sc->fdt_sc;
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sc = &fdt_sc->base;
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xi = (struct xlnx_pcib_irqsrc *)isrc;
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irq = xi->irq;
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if (irq < 32)
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msireg = XLNX_PCIE_RPMSIID1_MASK;
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else
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msireg = XLNX_PCIE_RPMSIID2_MASK;
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reg = bus_read_4(sc->res, msireg);
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if (mask)
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reg &= ~(1 << irq);
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else
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reg |= (1 << irq);
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bus_write_4(sc->res, msireg, reg);
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}
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static void
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xlnx_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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xlnx_pcib_msi_mask(dev, isrc, true);
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}
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static void
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xlnx_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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xlnx_pcib_msi_mask(dev, isrc, false);
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}
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static void
|
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xlnx_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc)
|
|
{
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|
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|
}
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|
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static void
|
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xlnx_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc)
|
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{
|
|
|
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xlnx_pcib_msi_mask(dev, isrc, false);
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|
}
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|
|
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static void
|
|
xlnx_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
|
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xlnx_pcib_msi_mask(dev, isrc, true);
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|
}
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|
|
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static int
|
|
xlnx_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
struct resource *res, struct intr_map_data *data)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xlnx_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
struct resource *res, struct intr_map_data *data)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t xlnx_pcib_fdt_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, xlnx_pcib_fdt_probe),
|
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DEVMETHOD(device_attach, xlnx_pcib_fdt_attach),
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|
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/* pcib interface */
|
|
DEVMETHOD(pcib_get_id, xlnx_pcib_fdt_get_id),
|
|
DEVMETHOD(pcib_read_config, xlnx_pcib_read_config),
|
|
DEVMETHOD(pcib_write_config, xlnx_pcib_write_config),
|
|
DEVMETHOD(pcib_alloc_msi, xlnx_pcib_alloc_msi),
|
|
DEVMETHOD(pcib_release_msi, xlnx_pcib_release_msi),
|
|
DEVMETHOD(pcib_map_msi, xlnx_pcib_map_msi),
|
|
|
|
/* MSI interface */
|
|
DEVMETHOD(msi_alloc_msi, xlnx_pcib_msi_alloc_msi),
|
|
DEVMETHOD(msi_release_msi, xlnx_pcib_msi_release_msi),
|
|
DEVMETHOD(msi_map_msi, xlnx_pcib_msi_map_msi),
|
|
|
|
/* Interrupt controller interface */
|
|
DEVMETHOD(pic_disable_intr, xlnx_pcib_msi_disable_intr),
|
|
DEVMETHOD(pic_enable_intr, xlnx_pcib_msi_enable_intr),
|
|
DEVMETHOD(pic_setup_intr, xlnx_pcib_msi_setup_intr),
|
|
DEVMETHOD(pic_teardown_intr, xlnx_pcib_msi_teardown_intr),
|
|
DEVMETHOD(pic_post_filter, xlnx_pcib_msi_post_filter),
|
|
DEVMETHOD(pic_post_ithread, xlnx_pcib_msi_post_ithread),
|
|
DEVMETHOD(pic_pre_ithread, xlnx_pcib_msi_pre_ithread),
|
|
|
|
/* End */
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
DEFINE_CLASS_1(pcib, xlnx_pcib_fdt_driver, xlnx_pcib_fdt_methods,
|
|
sizeof(struct xlnx_pcib_softc), generic_pcie_fdt_driver);
|
|
|
|
DRIVER_MODULE(xlnx_pcib, simplebus, xlnx_pcib_fdt_driver, 0, 0);
|
|
DRIVER_MODULE(xlnx_pcib, ofwbus, xlnx_pcib_fdt_driver, 0, 0);
|