765 lines
32 KiB
Modula-2
765 lines
32 KiB
Modula-2
/* This file contains the definitions and documentation for the
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Register Transfer Expressions (rtx's) that make up the
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Register Transfer Language (rtl) used in the Back End of the GNU compiler.
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Copyright (C) 1987, 1988, 1992, 1994 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Expression definitions and descriptions for all targets are in this file.
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Some will not be used for some targets.
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The fields in the cpp macro call "DEF_RTL_EXPR()"
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are used to create declarations in the C source of the compiler.
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The fields are:
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1. The internal name of the rtx used in the C source.
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It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
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By convention these are in UPPER_CASE.
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2. The name of the rtx in the external ASCII format read by
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read_rtx(), and printed by print_rtx().
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These names are stored in rtx_name[].
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By convention these are the internal (field 1) names in lower_case.
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3. The print format, and type of each rtx->fld[] (field) in this rtx.
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These formats are stored in rtx_format[].
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The meaning of the formats is documented in front of this array in rtl.c
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4. The class of the rtx. These are stored in rtx_class and are accessed
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via the GET_RTX_CLASS macro. They are defined as follows:
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"o" an rtx code that can be used to represent an object (e.g, REG, MEM)
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"<" an rtx code for a comparison (e.g, EQ, NE, LT)
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"1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
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"c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
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"3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
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"2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
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"b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
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"i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
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"m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
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"x" everything else
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*/
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/* ---------------------------------------------------------------------
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Expressions (and "meta" expressions) used for structuring the
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rtl representation of a program.
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--------------------------------------------------------------------- */
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/* an expression code name unknown to the reader */
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DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
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/* (NIL) is used by rtl reader and printer to represent a null pointer. */
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DEF_RTL_EXPR(NIL, "nil", "*", 'x')
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/* ---------------------------------------------------------------------
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Expressions used in constructing lists.
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--------------------------------------------------------------------- */
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/* a linked list of expressions */
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DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
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/* a linked list of instructions.
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The insns are represented in print by their uids. */
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DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
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/* ----------------------------------------------------------------------
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Expression types for machine descriptions.
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These do not appear in actual rtl code in the compiler.
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---------------------------------------------------------------------- */
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/* Appears only in machine descriptions.
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Means use the function named by the second arg (the string)
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as a predicate; if matched, store the structure that was matched
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in the operand table at index specified by the first arg (the integer).
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If the second arg is the null string, the structure is just stored.
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A third string argument indicates to the register allocator restrictions
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on where the operand can be allocated.
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If the target needs no restriction on any instruction this field should
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be the null string.
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The string is prepended by:
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'=' to indicate the operand is only written to.
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'+' to indicate the operand is both read and written to.
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Each character in the string represents an allocatable class for an operand.
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'g' indicates the operand can be any valid class.
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'i' indicates the operand can be immediate (in the instruction) data.
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'r' indicates the operand can be in a register.
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'm' indicates the operand can be in memory.
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'o' a subset of the 'm' class. Those memory addressing modes that
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can be offset at compile time (have a constant added to them).
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Other characters indicate target dependent operand classes and
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are described in each target's machine description.
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For instructions with more than one operand, sets of classes can be
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separated by a comma to indicate the appropriate multi-operand constraints.
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There must be a 1 to 1 correspondence between these sets of classes in
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all operands for an instruction.
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*/
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DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
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/* Appears only in machine descriptions.
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Means match a SCRATCH or a register. When used to generate rtl, a
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SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
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the desired mode and the first argument is the operand number.
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The second argument is the constraint. */
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DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
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/* Appears only in machine descriptions.
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Means match only something equal to what is stored in the operand table
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at the index specified by the argument. */
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DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
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/* Appears only in machine descriptions.
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Means apply a predicate, AND match recursively the operands of the rtx.
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Operand 0 is the operand-number, as in match_operand.
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Operand 1 is a predicate to apply (as a string, a function name).
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Operand 2 is a vector of expressions, each of which must match
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one subexpression of the rtx this construct is matching. */
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DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
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/* Appears only in machine descriptions.
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Means to match a PARALLEL of arbitrary length. The predicate is applied
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to the PARALLEL and the initial expressions in the PARALLEL are matched.
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Operand 0 is the operand-number, as in match_operand.
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Operand 1 is a predicate to apply to the PARALLEL.
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Operand 2 is a vector of expressions, each of which must match the
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corresponding element in the PARALLEL. */
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DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
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/* Appears only in machine descriptions.
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Means match only something equal to what is stored in the operand table
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at the index specified by the argument. For MATCH_OPERATOR. */
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DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
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/* Appears only in machine descriptions.
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Means match only something equal to what is stored in the operand table
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at the index specified by the argument. For MATCH_PARALLEL. */
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DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
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/* Appears only in machine descriptions.
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Defines the pattern for one kind of instruction.
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Operand:
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0: names this instruction.
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If the name is the null string, the instruction is in the
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machine description just to be recognized, and will never be emitted by
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the tree to rtl expander.
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1: is the pattern.
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2: is a string which is a C expression
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giving an additional condition for recognizing this pattern.
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A null string means no extra condition.
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3: is the action to execute if this pattern is matched.
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If this assembler code template starts with a * then it is a fragment of
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C code to run to decide on a template to use. Otherwise, it is the
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template to use.
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4: optionally, a vector of attributes for this insn.
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*/
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DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')
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/* Definition of a peephole optimization.
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1st operand: vector of insn patterns to match
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2nd operand: C expression that must be true
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3rd operand: template or C code to produce assembler output.
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4: optionally, a vector of attributes for this insn.
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*/
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DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')
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/* Definition of a split operation.
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1st operand: insn pattern to match
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2nd operand: C expression that must be true
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3rd operand: vector of insn patterns to place into a SEQUENCE
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4th operand: optionally, some C code to execute before generating the
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insns. This might, for example, create some RTX's and store them in
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elements of `recog_operand' for use by the vector of insn-patterns.
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(`operands' is an alias here for `recog_operand'). */
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DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
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/* Definition of a combiner pattern.
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Operands not defined yet. */
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DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
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/* Define how to generate multiple insns for a standard insn name.
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1st operand: the insn name.
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2nd operand: vector of insn-patterns.
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Use match_operand to substitute an element of `recog_operand'.
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3rd operand: C expression that must be true for this to be available.
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This may not test any operands.
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4th operand: Extra C code to execute before generating the insns.
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This might, for example, create some RTX's and store them in
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elements of `recog_operand' for use by the vector of insn-patterns.
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(`operands' is an alias here for `recog_operand'). */
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DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
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/* Define a requirement for delay slots.
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1st operand: Condition involving insn attributes that, if true,
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indicates that the insn requires the number of delay slots
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shown.
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2nd operand: Vector whose length is the three times the number of delay
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slots required.
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Each entry gives three conditions, each involving attributes.
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The first must be true for an insn to occupy that delay slot
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location. The second is true for all insns that can be
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annulled if the branch is true and the third is true for all
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insns that can be annulled if the branch is false.
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Multiple DEFINE_DELAYs may be present. They indicate differing
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requirements for delay slots. */
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DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
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/* Define a set of insns that requires a function unit. This means that
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these insns produce their result after a delay and that there may be
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restrictions on the number of insns of this type that can be scheduled
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simultaneously.
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More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
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Each gives a set of operations and associated delays. The first three
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operands must be the same for each operation for the same function unit.
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All delays are specified in cycles.
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1st operand: Name of function unit (mostly for documentation)
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2nd operand: Number of identical function units in CPU
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3rd operand: Total number of simultaneous insns that can execute on this
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function unit; 0 if unlimited.
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4th operand: Condition involving insn attribute, that, if true, specifies
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those insns that this expression applies to.
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5th operand: Constant delay after which insn result will be
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available.
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6th operand: Delay until next insn can be scheduled on the function unit
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executing this operation. The meaning depends on whether or
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not the next operand is supplied.
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7th operand: If this operand is not specified, the 6th operand gives the
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number of cycles after the instruction matching the 4th
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operand begins using the function unit until a subsequent
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insn can begin. A value of zero should be used for a
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unit with no issue constraints. If only one operation can
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be executed a time and the unit is busy for the entire time,
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the 3rd operand should be specified as 1, the 6th operand
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sould be specified as 0, and the 7th operand should not
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be specified.
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If this operand is specified, it is a list of attribute
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expressions. If an insn for which any of these expressions
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is true is currently executing on the function unit, the
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issue delay will be given by the 6th operand. Otherwise,
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the insn can be immediately scheduled (subject to the limit
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on the number of simultaneous operations executing on the
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unit.) */
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DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
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/* Define attribute computation for `asm' instructions. */
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DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
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/* SEQUENCE appears in the result of a `gen_...' function
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for a DEFINE_EXPAND that wants to make several insns.
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Its elements are the bodies of the insns that should be made.
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`emit_insn' takes the SEQUENCE apart and makes separate insns. */
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DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
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/* Refers to the address of its argument.
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This appears only in machine descriptions, indicating that
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any expression that would be acceptable as the operand of MEM
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should be matched. */
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DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
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/* ----------------------------------------------------------------------
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Expressions used for insn attributes. These also do not appear in
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actual rtl code in the compiler.
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---------------------------------------------------------------------- */
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/* Definition of an insn attribute.
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1st operand: name of the attribute
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2nd operand: comma-separated list of possible attribute values
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3rd operand: expression for the default value of the attribute. */
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DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
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/* Marker for the name of an attribute. */
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DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
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/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
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in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
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pattern.
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(set_attr "name" "value") is equivalent to
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(set (attr "name") (const_string "value")) */
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DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
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/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
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specify that attribute values are to be assigned according to the
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alternative matched.
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The following three expressions are equivalent:
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(set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
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(eq_attrq "alternative" "2") (const_string "a2")]
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(const_string "a3")))
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(set_attr_alternative "att" [(const_string "a1") (const_string "a2")
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(const_string "a3")])
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(set_attr "att" "a1,a2,a3")
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*/
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DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
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/* A conditional expression true if the value of the specified attribute of
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the current insn equals the specified value. The first operand is the
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attribute name and the second is the comparison value. */
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DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
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/* A conditional expression which is true if the specified flag is
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true for the insn being scheduled in reorg.
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genattr.c defines the following flags which can be tested by
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(attr_flag "foo") expressions in eligible_for_delay.
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forward, backward, very_likely, likely, very_unlikely, and unlikely. */
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DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
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/* ----------------------------------------------------------------------
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Expression types used for things in the instruction chain.
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All formats must start with "iuu" to handle the chain.
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Each insn expression holds an rtl instruction and its semantics
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during back-end processing.
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See macros's in "rtl.h" for the meaning of each rtx->fld[].
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---------------------------------------------------------------------- */
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/* An instruction that cannot jump. */
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DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
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/* An instruction that can possibly jump.
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Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
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DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')
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/* An instruction that can possibly call a subroutine
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but which will not change which instruction comes next
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in the current function.
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Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE.
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All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
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DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i')
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/* A marker that indicates that control will not flow through. */
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DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')
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/* Holds a label that is followed by instructions.
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Operand:
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3: is a number that is unique in the entire compilation.
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4: is the user-given name of the label, if any.
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5: is used in jump.c for the use-count of the label.
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and in flow.c to point to the chain of label_ref's to this label. */
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DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis0", 'x')
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/* Say where in the code a source line starts, for symbol table's sake.
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Contains a filename and a line number. Line numbers <= 0 are special:
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0 is used in a dummy placed at the front of every function
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just so there will never be a need to delete the first insn;
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-1 indicates a dummy; insns to be deleted by flow analysis and combining
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are really changed to NOTEs with a number of -1.
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-2 means beginning of a name binding contour; output N_LBRAC.
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-3 means end of a contour; output N_RBRAC. */
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DEF_RTL_EXPR(NOTE, "note", "iuusn", 'x')
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/* INLINE_HEADER is use by inline function machinery. The information
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it contains helps to build the mapping function between the rtx's of
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the function to be inlined and the current function being expanded. */
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DEF_RTL_EXPR(INLINE_HEADER, "inline_header", "iuuuiiiiiieiiEe", 'x')
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/* ----------------------------------------------------------------------
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Top level constituents of INSN, JUMP_INSN and CALL_INSN.
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---------------------------------------------------------------------- */
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/* Several operations to be done in parallel. */
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DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
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/* A string that is passed through to the assembler as input.
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One can obviously pass comments through by using the
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assembler comment syntax.
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These occur in an insn all by themselves as the PATTERN.
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They also appear inside an ASM_OPERANDS
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as a convenient way to hold a string. */
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DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
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/* An assembler instruction with operands.
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1st operand is the instruction template.
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2nd operand is the constraint for the output.
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3rd operand is the number of the output this expression refers to.
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When an insn stores more than one value, a separate ASM_OPERANDS
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is made for each output; this integer distinguishes them.
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4th is a vector of values of input operands.
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5th is a vector of modes and constraints for the input operands.
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Each element is an ASM_INPUT containing a constraint string
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and whose mode indicates the mode of the input operand.
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6th is the name of the containing source file.
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7th is the source line number. */
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DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
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/* A machine-specific operation.
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1st operand is a vector of operands being used by the operation so that
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any needed reloads can be done.
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2nd operand is a unique value saying which of a number of machine-specific
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operations is to be performed.
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(Note that the vector must be the first operand because of the way that
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genrecog.c record positions within an insn.)
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This can occur all by itself in a PATTERN, as a component of a PARALLEL,
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or inside an expression. */
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DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
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/* Similar, but a volatile operation and one which may trap. */
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DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
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/* Vector of addresses, stored as full words. */
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/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
|
|
DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
|
|
|
|
/* Vector of address differences X0 - BASE, X1 - BASE, ...
|
|
First operand is BASE; the vector contains the X's.
|
|
The machine mode of this rtx says how much space to leave
|
|
for each difference. */
|
|
DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eE", 'x')
|
|
|
|
/* ----------------------------------------------------------------------
|
|
At the top level of an instruction (perhaps under PARALLEL).
|
|
---------------------------------------------------------------------- */
|
|
|
|
/* Assignment.
|
|
Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
|
|
Operand 2 is the value stored there.
|
|
ALL assignment must use SET.
|
|
Instructions that do multiple assignments must use multiple SET,
|
|
under PARALLEL. */
|
|
DEF_RTL_EXPR(SET, "set", "ee", 'x')
|
|
|
|
/* Indicate something is used in a way that we don't want to explain.
|
|
For example, subroutine calls will use the register
|
|
in which the static chain is passed. */
|
|
DEF_RTL_EXPR(USE, "use", "e", 'x')
|
|
|
|
/* Indicate something is clobbered in a way that we don't want to explain.
|
|
For example, subroutine calls will clobber some physical registers
|
|
(the ones that are by convention not saved). */
|
|
DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
|
|
|
|
/* Call a subroutine.
|
|
Operand 1 is the address to call.
|
|
Operand 2 is the number of arguments. */
|
|
|
|
DEF_RTL_EXPR(CALL, "call", "ee", 'x')
|
|
|
|
/* Return from a subroutine. */
|
|
|
|
DEF_RTL_EXPR(RETURN, "return", "", 'x')
|
|
|
|
/* Conditional trap.
|
|
Operand 1 is the condition.
|
|
Operand 2 is the trap code.
|
|
For an unconditional trap, make the condition (const_int 1). */
|
|
DEF_RTL_EXPR(TRAP_IF, "trap_if", "ei", 'x')
|
|
|
|
/* ----------------------------------------------------------------------
|
|
Primitive values for use in expressions.
|
|
---------------------------------------------------------------------- */
|
|
|
|
/* numeric integer constant */
|
|
DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
|
|
|
|
/* numeric double constant.
|
|
Operand 0 is the MEM that stores this constant in memory,
|
|
or various other things (see comments at immed_double_const in varasm.c).
|
|
Operand 1 is a chain of all CONST_DOUBLEs in use in the current function.
|
|
Remaining operands hold the actual value.
|
|
The number of operands may be more than 2 if cross-compiling;
|
|
see init_rtl. */
|
|
DEF_RTL_EXPR(CONST_DOUBLE, "const_double", "e0ww", 'o')
|
|
|
|
/* String constant. Used only for attributes right now. */
|
|
DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
|
|
|
|
/* This is used to encapsulate an expression whose value is constant
|
|
(such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
|
|
recognized as a constant operand rather than by arithmetic instructions. */
|
|
|
|
DEF_RTL_EXPR(CONST, "const", "e", 'o')
|
|
|
|
/* program counter. Ordinary jumps are represented
|
|
by a SET whose first operand is (PC). */
|
|
DEF_RTL_EXPR(PC, "pc", "", 'o')
|
|
|
|
/* A register. The "operand" is the register number, accessed
|
|
with the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
|
|
than a hardware register is being referred to. */
|
|
DEF_RTL_EXPR(REG, "reg", "i", 'o')
|
|
|
|
/* A scratch register. This represents a register used only within a
|
|
single insn. It will be turned into a REG during register allocation
|
|
or reload unless the constraint indicates that the register won't be
|
|
needed, in which case it can remain a SCRATCH. This code is
|
|
marked as having one operand so it can be turned into a REG. */
|
|
DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
|
|
|
|
/* One word of a multi-word value.
|
|
The first operand is the complete value; the second says which word.
|
|
The WORDS_BIG_ENDIAN flag controls whether word number 0
|
|
(as numbered in a SUBREG) is the most or least significant word.
|
|
|
|
This is also used to refer to a value in a different machine mode.
|
|
For example, it can be used to refer to a SImode value as if it were
|
|
Qimode, or vice versa. Then the word number is always 0. */
|
|
DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
|
|
|
|
/* This one-argument rtx is used for move instructions
|
|
that are guaranteed to alter only the low part of a destination.
|
|
Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
|
|
has an unspecified effect on the high part of REG,
|
|
but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
|
|
is guaranteed to alter only the bits of REG that are in HImode.
|
|
|
|
The actual instruction used is probably the same in both cases,
|
|
but the register constraints may be tighter when STRICT_LOW_PART
|
|
is in use. */
|
|
|
|
DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
|
|
|
|
/* (CONCAT a b) represents the virtual concatenation of a and b
|
|
to make a value that has as many bits as a and b put together.
|
|
This is used for complex values. Normally it appears only
|
|
in DECL_RTLs and during RTL generation, but not in the insn chain. */
|
|
DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
|
|
|
|
/* A memory location; operand is the address.
|
|
Can be nested inside a VOLATILE. */
|
|
DEF_RTL_EXPR(MEM, "mem", "e", 'o')
|
|
|
|
/* Reference to an assembler label in the code for this function.
|
|
The operand is a CODE_LABEL found in the insn chain.
|
|
The unprinted fields 1 and 2 are used in flow.c for the
|
|
LABEL_NEXTREF and CONTAINING_INSN. */
|
|
DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
|
|
|
|
/* Reference to a named label: the string that is the first operand,
|
|
with `_' added implicitly in front.
|
|
Exception: if the first character explicitly given is `*',
|
|
to give it to the assembler, remove the `*' and do not add `_'. */
|
|
DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
|
|
|
|
/* The condition code register is represented, in our imagination,
|
|
as a register holding a value that can be compared to zero.
|
|
In fact, the machine has already compared them and recorded the
|
|
results; but instructions that look at the condition code
|
|
pretend to be looking at the entire value and comparing it. */
|
|
DEF_RTL_EXPR(CC0, "cc0", "", 'o')
|
|
|
|
/* =====================================================================
|
|
A QUEUED expression really points to a member of the queue of instructions
|
|
to be output later for postincrement/postdecrement.
|
|
QUEUED expressions never become part of instructions.
|
|
When a QUEUED expression would be put into an instruction,
|
|
instead either the incremented variable or a copy of its previous
|
|
value is used.
|
|
|
|
Operands are:
|
|
0. the variable to be incremented (a REG rtx).
|
|
1. the incrementing instruction, or 0 if it hasn't been output yet.
|
|
2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
|
|
3. the body to use for the incrementing instruction
|
|
4. the next QUEUED expression in the queue.
|
|
====================================================================== */
|
|
|
|
DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
|
|
|
|
/* ----------------------------------------------------------------------
|
|
Expressions for operators in an rtl pattern
|
|
---------------------------------------------------------------------- */
|
|
|
|
/* if_then_else. This is used in representing ordinary
|
|
conditional jump instructions.
|
|
Operand:
|
|
0: condition
|
|
1: then expr
|
|
2: else expr */
|
|
DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
|
|
|
|
/* General conditional. The first operand is a vector composed of pairs of
|
|
expressions. The first element of each pair is evaluated, in turn.
|
|
The value of the conditional is the second expression of the first pair
|
|
whose first expression evaluates non-zero. If none of the expressions is
|
|
true, the second operand will be used as the value of the conditional.
|
|
|
|
This should be replaced with use of IF_THEN_ELSE. */
|
|
DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
|
|
|
|
/* Comparison, produces a condition code result. */
|
|
DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
|
|
|
|
/* plus */
|
|
DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
|
|
|
|
/* Operand 0 minus operand 1. */
|
|
DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
|
|
|
|
/* Minus operand 0. */
|
|
DEF_RTL_EXPR(NEG, "neg", "e", '1')
|
|
|
|
DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
|
|
|
|
/* Operand 0 divided by operand 1. */
|
|
DEF_RTL_EXPR(DIV, "div", "ee", '2')
|
|
/* Remainder of operand 0 divided by operand 1. */
|
|
DEF_RTL_EXPR(MOD, "mod", "ee", '2')
|
|
|
|
/* Unsigned divide and remainder. */
|
|
DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
|
|
DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
|
|
|
|
/* Bitwise operations. */
|
|
DEF_RTL_EXPR(AND, "and", "ee", 'c')
|
|
|
|
DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
|
|
|
|
DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
|
|
|
|
DEF_RTL_EXPR(NOT, "not", "e", '1')
|
|
|
|
/* Operand:
|
|
0: value to be shifted.
|
|
1: number of bits. */
|
|
DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2')
|
|
DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2')
|
|
|
|
/* Right shift operations, for machines where these are not the same
|
|
as left shifting with a negative argument. */
|
|
|
|
DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2')
|
|
DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2')
|
|
DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2')
|
|
|
|
/* Minimum and maximum values of two operands. We need both signed and
|
|
unsigned forms. (We cannot use MIN for SMIN because it conflicts
|
|
with a macro of the same name.) */
|
|
|
|
DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
|
|
DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
|
|
DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
|
|
DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
|
|
|
|
/* These unary operations are used to represent incrementation
|
|
and decrementation as they occur in memory addresses.
|
|
The amount of increment or decrement are not represented
|
|
because they can be understood from the machine-mode of the
|
|
containing MEM. These operations exist in only two cases:
|
|
1. pushes onto the stack.
|
|
2. created automatically by the life_analysis pass in flow.c. */
|
|
DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x')
|
|
DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x')
|
|
DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x')
|
|
DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x')
|
|
|
|
/* Comparison operations. The ordered comparisons exist in two
|
|
flavors, signed and unsigned. */
|
|
DEF_RTL_EXPR(NE, "ne", "ee", '<')
|
|
DEF_RTL_EXPR(EQ, "eq", "ee", '<')
|
|
DEF_RTL_EXPR(GE, "ge", "ee", '<')
|
|
DEF_RTL_EXPR(GT, "gt", "ee", '<')
|
|
DEF_RTL_EXPR(LE, "le", "ee", '<')
|
|
DEF_RTL_EXPR(LT, "lt", "ee", '<')
|
|
DEF_RTL_EXPR(GEU, "geu", "ee", '<')
|
|
DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
|
|
DEF_RTL_EXPR(LEU, "leu", "ee", '<')
|
|
DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
|
|
|
|
/* Represents the result of sign-extending the sole operand.
|
|
The machine modes of the operand and of the SIGN_EXTEND expression
|
|
determine how much sign-extension is going on. */
|
|
DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
|
|
|
|
/* Similar for zero-extension (such as unsigned short to int). */
|
|
DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
|
|
|
|
/* Similar but here the operand has a wider mode. */
|
|
DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
|
|
|
|
/* Similar for extending floating-point values (such as SFmode to DFmode). */
|
|
DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
|
|
DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
|
|
|
|
/* Conversion of fixed point operand to floating point value. */
|
|
DEF_RTL_EXPR(FLOAT, "float", "e", '1')
|
|
|
|
/* With fixed-point machine mode:
|
|
Conversion of floating point operand to fixed point value.
|
|
Value is defined only when the operand's value is an integer.
|
|
With floating-point machine mode (and operand with same mode):
|
|
Operand is rounded toward zero to produce an integer value
|
|
represented in floating point. */
|
|
DEF_RTL_EXPR(FIX, "fix", "e", '1')
|
|
|
|
/* Conversion of unsigned fixed point operand to floating point value. */
|
|
DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
|
|
|
|
/* With fixed-point machine mode:
|
|
Conversion of floating point operand to *unsigned* fixed point value.
|
|
Value is defined only when the operand's value is an integer. */
|
|
DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
|
|
|
|
/* Absolute value */
|
|
DEF_RTL_EXPR(ABS, "abs", "e", '1')
|
|
|
|
/* Square root */
|
|
DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
|
|
|
|
/* Find first bit that is set.
|
|
Value is 1 + number of trailing zeros in the arg.,
|
|
or 0 if arg is 0. */
|
|
DEF_RTL_EXPR(FFS, "ffs", "e", '1')
|
|
|
|
/* Reference to a signed bit-field of specified size and position.
|
|
Operand 0 is the memory unit (usually SImode or QImode) which
|
|
contains the field's first bit. Operand 1 is the width, in bits.
|
|
Operand 2 is the number of bits in the memory unit before the
|
|
first bit of this field.
|
|
If BITS_BIG_ENDIAN is defined, the first bit is the msb and
|
|
operand 2 counts from the msb of the memory unit.
|
|
Otherwise, the first bit is the lsb and operand 2 counts from
|
|
the lsb of the memory unit. */
|
|
DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
|
|
|
|
/* Similar for unsigned bit-field. */
|
|
DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
|
|
|
|
/* For RISC machines. These save memory when splitting insns. */
|
|
|
|
/* HIGH are the high-order bits of a constant expression. */
|
|
DEF_RTL_EXPR(HIGH, "high", "e", 'o')
|
|
|
|
/* LO_SUM is the sum of a register and the low-order bits
|
|
of a constant expression. */
|
|
DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
|
|
|
|
/*
|
|
Local variables:
|
|
mode:c
|
|
version-control: t
|
|
End:
|
|
*/
|