bc96dccc69
- Use isync/lwsync unconditionally for acquire/release. Use of isync guarantees a complete memory barrier, which is important for serialization of bus space accesses with mutexes on multi-processor systems. - Go back to using sync as the I/O memory barrier, which solves the same problem as above with respect to mutex release using lwsync, while not penalizing non-I/O operations like a return to sync on the atomic release operations would. - Place an acquisition barrier around thread lock acquisition in cpu_switchin().
288 lines
8.7 KiB
ArmAsm
288 lines
8.7 KiB
ArmAsm
/* $FreeBSD$ */
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/* $NetBSD: locore.S,v 1.24 2000/05/31 05:09:17 thorpej Exp $ */
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/*-
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* Copyright (C) 2001 Benno Rice
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "assym.s"
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#include "opt_sched.h"
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#include <sys/syscall.h>
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#include <machine/trap.h>
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#include <machine/param.h>
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#include <machine/asm.h>
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/*
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* void cpu_throw(struct thread *old, struct thread *new)
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*/
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ENTRY(cpu_throw)
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mr %r13, %r4
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b cpu_switchin
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/*
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* void cpu_switch(struct thread *old,
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* struct thread *new,
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* struct mutex *mtx);
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*
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* Switch to a new thread saving the current state in the old thread.
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*/
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ENTRY(cpu_switch)
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ld %r6,TD_PCB(%r3) /* Get the old thread's PCB ptr */
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std %r12,PCB_CONTEXT(%r6) /* Save the non-volatile GP regs.
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These can now be used for scratch */
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std %r14,PCB_CONTEXT+2*8(%r6)
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std %r15,PCB_CONTEXT+3*8(%r6)
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std %r16,PCB_CONTEXT+4*8(%r6)
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std %r17,PCB_CONTEXT+5*8(%r6)
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std %r18,PCB_CONTEXT+6*8(%r6)
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std %r19,PCB_CONTEXT+7*8(%r6)
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std %r20,PCB_CONTEXT+8*8(%r6)
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std %r21,PCB_CONTEXT+9*8(%r6)
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std %r22,PCB_CONTEXT+10*8(%r6)
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std %r23,PCB_CONTEXT+11*8(%r6)
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std %r24,PCB_CONTEXT+12*8(%r6)
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std %r25,PCB_CONTEXT+13*8(%r6)
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std %r26,PCB_CONTEXT+14*8(%r6)
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std %r27,PCB_CONTEXT+15*8(%r6)
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std %r28,PCB_CONTEXT+16*8(%r6)
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std %r29,PCB_CONTEXT+17*8(%r6)
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std %r30,PCB_CONTEXT+18*8(%r6)
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std %r31,PCB_CONTEXT+19*8(%r6)
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mfcr %r16 /* Save the condition register */
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std %r16,PCB_CR(%r6)
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mflr %r16 /* Save the link register */
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std %r16,PCB_LR(%r6)
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std %r1,PCB_SP(%r6) /* Save the stack pointer */
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std %r2,PCB_TOC(%r6) /* Save the TOC pointer */
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mr %r14,%r3 /* Copy the old thread ptr... */
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mr %r13,%r4 /* and the new thread ptr in curthread*/
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mr %r16,%r5 /* and the new lock */
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mr %r17,%r6 /* and the PCB */
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stdu %r1,-48(%r1)
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lwz %r7,PCB_FLAGS(%r17)
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/* Save FPU context if needed */
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andi. %r7, %r7, PCB_FPU
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beq .L1
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bl save_fpu
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nop
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.L1:
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mr %r3,%r14 /* restore old thread ptr */
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lwz %r7,PCB_FLAGS(%r17)
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/* Save Altivec context if needed */
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andi. %r7, %r7, PCB_VEC
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beq .L2
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bl save_vec
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nop
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.L2:
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mr %r3,%r14 /* restore old thread ptr */
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bl pmap_deactivate /* Deactivate the current pmap */
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nop
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addi %r1,%r1,48
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sync /* Make sure all of that finished */
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std %r16,TD_LOCK(%r14) /* ULE: update old thread's lock */
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cpu_switchin:
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#if defined(SMP) && defined(SCHED_ULE)
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/* Wait for the new thread to become unblocked */
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lis %r6,blocked_lock@ha
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addi %r6,%r6,blocked_lock@l
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blocked_loop:
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ld %r7,TD_LOCK(%r13)
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cmpd %r6,%r7
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beq- blocked_loop
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isync
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#endif
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mfsprg %r7,0 /* Get the pcpu pointer */
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std %r13,PC_CURTHREAD(%r7) /* Store new current thread */
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ld %r17,TD_PCB(%r13) /* Store new current PCB */
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std %r17,PC_CURPCB(%r7)
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stdu %r1,-48(%r1)
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mr %r3,%r13 /* Get new thread ptr */
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bl pmap_activate /* Activate the new address space */
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nop
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lwz %r6, PCB_FLAGS(%r17)
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/* Restore FPU context if needed */
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andi. %r6, %r6, PCB_FPU
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beq .L3
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mr %r3,%r13 /* Pass curthread to enable_fpu */
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bl enable_fpu
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nop
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.L3:
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lwz %r6, PCB_FLAGS(%r17)
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/* Restore Altivec context if needed */
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andi. %r6, %r6, PCB_VEC
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beq .L4
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mr %r3,%r13 /* Pass curthread to enable_vec */
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bl enable_vec
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nop
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/* thread to restore is in r3 */
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.L4:
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addi %r1,%r1,48
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mr %r3,%r17 /* Recover PCB ptr */
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ld %r12,PCB_CONTEXT(%r3) /* Load the non-volatile GP regs. */
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ld %r14,PCB_CONTEXT+2*8(%r3)
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ld %r15,PCB_CONTEXT+3*8(%r3)
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ld %r16,PCB_CONTEXT+4*8(%r3)
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ld %r17,PCB_CONTEXT+5*8(%r3)
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ld %r18,PCB_CONTEXT+6*8(%r3)
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ld %r19,PCB_CONTEXT+7*8(%r3)
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ld %r20,PCB_CONTEXT+8*8(%r3)
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ld %r21,PCB_CONTEXT+9*8(%r3)
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ld %r22,PCB_CONTEXT+10*8(%r3)
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ld %r23,PCB_CONTEXT+11*8(%r3)
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ld %r24,PCB_CONTEXT+12*8(%r3)
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ld %r25,PCB_CONTEXT+13*8(%r3)
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ld %r26,PCB_CONTEXT+14*8(%r3)
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ld %r27,PCB_CONTEXT+15*8(%r3)
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ld %r28,PCB_CONTEXT+16*8(%r3)
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ld %r29,PCB_CONTEXT+17*8(%r3)
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ld %r30,PCB_CONTEXT+18*8(%r3)
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ld %r31,PCB_CONTEXT+19*8(%r3)
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ld %r5,PCB_CR(%r3) /* Load the condition register */
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mtcr %r5
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ld %r5,PCB_LR(%r3) /* Load the link register */
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mtlr %r5
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ld %r1,PCB_SP(%r3) /* Load the stack pointer */
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ld %r2,PCB_TOC(%r3) /* Load the TOC pointer */
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lis %r5,USER_ADDR@highesta /* Load the copyin/out segment reg */
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ori %r5,%r5,USER_ADDR@highera
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sldi %r5,%r5,32
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oris %r5,%r5,USER_ADDR@ha
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isync
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slbie %r5
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lis %r6,USER_SLB_SLBE@highesta
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ori %r6,%r6,USER_SLB_SLBE@highera
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sldi %r6,%r6,32
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oris %r6,%r6,USER_SLB_SLBE@ha
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ori %r6,%r6,USER_SLB_SLBE@l
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ld %r5,PCB_AIM_USR_VSID(%r3)
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slbmte %r5,%r6
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isync
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/*
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* Perform a dummy stdcx. to clear any reservations we may have
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* inherited from the previous thread. It doesn't matter if the
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* stdcx succeeds or not. pcb_context[0] can be clobbered.
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*/
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stdcx. %r1, 0, %r3
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blr
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/*
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* savectx(pcb)
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* Update pcb, saving current processor state
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*/
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ENTRY(savectx)
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std %r12,PCB_CONTEXT(%r3) /* Save the non-volatile GP regs. */
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std %r13,PCB_CONTEXT+1*8(%r3)
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std %r14,PCB_CONTEXT+2*8(%r3)
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std %r15,PCB_CONTEXT+3*8(%r3)
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std %r16,PCB_CONTEXT+4*8(%r3)
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std %r17,PCB_CONTEXT+5*8(%r3)
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std %r18,PCB_CONTEXT+6*8(%r3)
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std %r19,PCB_CONTEXT+7*8(%r3)
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std %r20,PCB_CONTEXT+8*8(%r3)
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std %r21,PCB_CONTEXT+9*8(%r3)
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std %r22,PCB_CONTEXT+10*8(%r3)
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std %r23,PCB_CONTEXT+11*8(%r3)
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std %r24,PCB_CONTEXT+12*8(%r3)
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std %r25,PCB_CONTEXT+13*8(%r3)
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std %r26,PCB_CONTEXT+14*8(%r3)
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std %r27,PCB_CONTEXT+15*8(%r3)
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std %r28,PCB_CONTEXT+16*8(%r3)
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std %r29,PCB_CONTEXT+17*8(%r3)
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std %r30,PCB_CONTEXT+18*8(%r3)
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std %r31,PCB_CONTEXT+19*8(%r3)
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mfcr %r4 /* Save the condition register */
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std %r4,PCB_CR(%r3)
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std %r2,PCB_TOC(%r3) /* Save the TOC pointer */
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blr
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/*
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* fork_trampoline()
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* Set up the return from cpu_fork()
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*/
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ENTRY_NOPROF(fork_trampoline)
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ld %r3,CF_FUNC(%r1)
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ld %r4,CF_ARG0(%r1)
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ld %r5,CF_ARG1(%r1)
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stdu %r1,-48(%r1)
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bl fork_exit
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nop
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addi %r1,%r1,48+CF_SIZE-FSP /* Allow 8 bytes in front of
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trapframe to simulate FRAME_SETUP
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does when allocating space for
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a frame pointer/saved LR */
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b trapexit
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nop
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