b09de0b34a
ARM Coresight is a solution for debug and trace of complex SoC designs. This includes a collection of drivers for ARM Coresight interconnect devices within a small Coresight framework. Supported devices are: o Embedded Trace Macrocell v4 (ETMv4) o Funnel o Dynamic Replicator o Trace Memory Controller (TMC) o CPU debug module Devices are connected to each other internally in SoC and the configuration of each device endpoints is described in FDT. Typical trace flow (as found on Qualcomm Snapdragon 410e): CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM CPU1 -> ETM1 -^ CPU2 -> ETM2 -^ CPU3 -> ETM3 -^ Note that both Embedded Trace FIFO (ETF) and Embedded Trace Router (ETR) are hardware configurations of TMC. This is required for upcoming HWPMC tracing support. This is tested on single-core system only. Reviewed by: andrew (partially) Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D14618
165 lines
4.2 KiB
C
165 lines
4.2 KiB
C
/*-
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* Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by BAE Systems, the University of Cambridge
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* Computer Laboratory, and Memorial University under DARPA/AFRL contract
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* FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
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* (TC) research program.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm64/coresight/coresight.h>
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#include "coresight_if.h"
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#define EDPCSR 0x0a0
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#define EDCIDSR 0x0a4
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#define EDVIDSR 0x0a8
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#define EDPCSR_HI 0x0ac
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#define EDOSLAR 0x300
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#define EDPRCR 0x310
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#define EDPRCR_COREPURQ (1 << 3)
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#define EDPRCR_CORENPDRQ (1 << 0)
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#define EDPRSR 0x314
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#define EDDEVID1 0xfc4
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#define EDDEVID 0xfc8
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static struct ofw_compat_data compat_data[] = {
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{ "arm,coresight-cpu-debug", 1 },
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{ NULL, 0 }
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};
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struct debug_softc {
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struct resource *res;
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struct coresight_platform_data *pdata;
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};
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static struct resource_spec debug_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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debug_init(device_t dev)
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{
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struct debug_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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/* Unlock Coresight */
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bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);
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/* Unlock Debug */
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bus_write_4(sc->res, EDOSLAR, 0);
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/* Already initialized? */
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reg = bus_read_4(sc->res, EDPRCR);
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if (reg & EDPRCR_CORENPDRQ)
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return (0);
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/* Enable power */
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reg |= EDPRCR_COREPURQ;
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bus_write_4(sc->res, EDPRCR, reg);
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do {
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reg = bus_read_4(sc->res, EDPRSR);
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} while ((reg & EDPRCR_CORENPDRQ) == 0);
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return (0);
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}
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static int
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debug_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Coresight CPU Debug");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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debug_attach(device_t dev)
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{
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struct coresight_desc desc;
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struct debug_softc *sc;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, debug_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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sc->pdata = coresight_get_platform_data(dev);
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desc.pdata = sc->pdata;
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desc.dev = dev;
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desc.dev_type = CORESIGHT_CPU_DEBUG;
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coresight_register(&desc);
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return (0);
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}
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static device_method_t debug_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, debug_probe),
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DEVMETHOD(device_attach, debug_attach),
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/* Coresight interface */
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DEVMETHOD(coresight_init, debug_init),
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DEVMETHOD_END
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};
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static driver_t debug_driver = {
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"debug",
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debug_methods,
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sizeof(struct debug_softc),
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};
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static devclass_t debug_devclass;
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EARLY_DRIVER_MODULE(debug, simplebus, debug_driver, debug_devclass,
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0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LATE);
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MODULE_VERSION(debug, 1);
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