864092bcaa
ARM and MIPS fail universe builds. ARM and MIPS are missing the following: * VM_MEMATTR_WRITE_THROUGH * VM_MEMATTR_WRITE_COMBINING Pointy-hat to: jhibbits
263 lines
5.9 KiB
C
263 lines
5.9 KiB
C
/*-
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* Copyright (c) 2010 Isilon Systems, Inc.
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* Copyright (c) 2010 iX Systems, Inc.
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* Copyright (c) 2010 Panasas, Inc.
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* Copyright (c) 2013-2015 Mellanox Technologies, Ltd.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _LINUX_IO_H_
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#define _LINUX_IO_H_
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#include <machine/vm.h>
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#include <sys/endian.h>
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#include <sys/types.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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static inline uint32_t
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__raw_readl(const volatile void *addr)
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{
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return *(const volatile uint32_t *)addr;
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}
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static inline void
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__raw_writel(uint32_t b, volatile void *addr)
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{
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*(volatile uint32_t *)addr = b;
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}
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static inline uint64_t
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__raw_readq(const volatile void *addr)
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{
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return *(const volatile uint64_t *)addr;
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}
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static inline void
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__raw_writeq(uint64_t b, volatile void *addr)
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{
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*(volatile uint64_t *)addr = b;
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}
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/*
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* XXX This is all x86 specific. It should be bus space access.
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*/
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#define mmiowb() barrier()
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#undef writel
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static inline void
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writel(uint32_t b, void *addr)
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{
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*(volatile uint32_t *)addr = b;
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}
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#undef writeq
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static inline void
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writeq(uint64_t b, void *addr)
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{
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*(volatile uint64_t *)addr = b;
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}
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#undef writeb
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static inline void
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writeb(uint8_t b, void *addr)
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{
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*(volatile uint8_t *)addr = b;
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}
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#undef writew
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static inline void
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writew(uint16_t b, void *addr)
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{
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*(volatile uint16_t *)addr = b;
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}
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#undef ioread8
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static inline uint8_t
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ioread8(const volatile void *addr)
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{
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return *(const volatile uint8_t *)addr;
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}
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#undef ioread16
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static inline uint16_t
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ioread16(const volatile void *addr)
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{
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return *(const volatile uint16_t *)addr;
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}
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#undef ioread32
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static inline uint32_t
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ioread32(const volatile void *addr)
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{
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return *(const volatile uint32_t *)addr;
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}
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#undef ioread32be
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static inline uint32_t
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ioread32be(const volatile void *addr)
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{
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return be32toh(*(const volatile uint32_t *)addr);
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}
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#undef iowrite8
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static inline void
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iowrite8(uint8_t v, volatile void *addr)
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{
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*(volatile uint8_t *)addr = v;
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}
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#undef iowrite16
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static inline void
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iowrite16(uint16_t v, volatile void *addr)
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{
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*(volatile uint16_t *)addr = v;
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}
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#undef iowrite32
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static inline void
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iowrite32(uint32_t v, volatile void *addr)
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{
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*(volatile uint32_t *)addr = v;
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}
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#undef iowrite32be
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static inline void
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iowrite32be(uint32_t v, volatile void *addr)
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{
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*(volatile uint32_t *)addr = htobe32(v);
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}
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#undef readb
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static inline uint8_t
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readb(const volatile void *addr)
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{
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return *(const volatile uint8_t *)addr;
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}
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#undef readw
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static inline uint16_t
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readw(const volatile void *addr)
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{
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return *(const volatile uint16_t *)addr;
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}
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#undef readl
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static inline uint32_t
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readl(const volatile void *addr)
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{
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return *(const volatile uint32_t *)addr;
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}
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#if defined(__i386__) || defined(__amd64__)
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static inline void
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_outb(u_char data, u_int port)
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{
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__asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
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}
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#endif
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#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
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void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr);
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#else
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#define _ioremap_attr(...) NULL
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#endif
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#define ioremap_nocache(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
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#define ioremap_wc(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING)
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#define ioremap_wb(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_WRITE_BACK)
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#define ioremap_wt(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_WRITE_THROUGH)
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#define ioremap(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
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void iounmap(void *addr);
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#define memset_io(a, b, c) memset((a), (b), (c))
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#define memcpy_fromio(a, b, c) memcpy((a), (b), (c))
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#define memcpy_toio(a, b, c) memcpy((a), (b), (c))
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static inline void
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__iowrite32_copy(void *to, void *from, size_t count)
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{
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uint32_t *src;
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uint32_t *dst;
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int i;
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for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
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__raw_writel(*src, dst);
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}
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static inline void
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__iowrite64_copy(void *to, void *from, size_t count)
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{
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#ifdef __LP64__
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uint64_t *src;
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uint64_t *dst;
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int i;
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for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
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__raw_writeq(*src, dst);
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#else
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__iowrite32_copy(to, from, count * 2);
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#endif
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}
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enum {
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MEMREMAP_WB = 1 << 0,
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MEMREMAP_WT = 1 << 1,
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MEMREMAP_WC = 1 << 2,
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};
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static inline void *
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memremap(resource_size_t offset, size_t size, unsigned long flags)
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{
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void *addr = NULL;
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if ((flags & MEMREMAP_WB) &&
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(addr = ioremap_wb(offset, size)) != NULL)
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goto done;
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if ((flags & MEMREMAP_WT) &&
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(addr = ioremap_wt(offset, size)) != NULL)
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goto done;
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if ((flags & MEMREMAP_WC) &&
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(addr = ioremap_wc(offset, size)) != NULL)
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goto done;
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done:
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return (addr);
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}
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static inline void
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memunmap(void *addr)
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{
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/* XXX May need to check if this is RAM */
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iounmap(addr);
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}
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#endif /* _LINUX_IO_H_ */
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