343 lines
11 KiB
C
343 lines
11 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/smp.h>
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#include <sys/pcpu.h>
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#include <mips/rmi/xlrconfig.h>
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#include <mips/rmi/perfmon_xlrconfig.h>
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#include <mips/rmi/perfmon.h>
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#include <mips/rmi/perfmon_utils.h>
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#include <mips/rmi/pic.h>
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#include <mips/rmi/msgring.h>
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#define CC_SAMPLE (PERF_CP2_CREDITS <<24)
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#define CC_REG0 16
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#define CC_REG1 17
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#define CC_REG2 18
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#define CC_REG3 19
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#define CC_REG4 20
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#define CC_REG5 21
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#define CC_REG6 22
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#define CC_REG7 23
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#define CC_REG8 24
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#define CC_REG9 25
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#define CC_REG10 26
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#define CC_REG11 27
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#define CC_REG12 28
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#define CC_REG13 29
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#define CC_REG14 30
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#define CC_REG15 31
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extern uint32_t cpu_ltop_map[MAXCPU];
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extern struct perf_area *xlr_shared_config_area;
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static __inline__ uint32_t
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make_cpu_tag(uint32_t val)
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{
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return PERF_CP0_COUNTER << 24 | (val & 0xffff);
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}
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static __inline__ uint32_t
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make_cp0_perf_control(uint32_t flags, uint32_t thread, uint32_t event)
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{
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return (flags & 0x1f) | (thread & 0x03) << 11 | (event & 0x3f) << 5 | 0x01;
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}
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static __inline__ uint32_t
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cp0_perf_control_get_thread(uint32_t control_word)
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{
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return (control_word & 0x1800) >> 11;
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}
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static __inline__ uint32_t
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cp0_perf_control_get_event(uint32_t control_word)
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{
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return (control_word & 0x7e0) >> 5;
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}
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static __inline__ uint32_t
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read_pic_6_timer_count(void)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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/* PIC counts down, convert it to count up */
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return 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
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}
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static uint32_t
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get_num_events(const uint64_t * events)
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{
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int total = 0;
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int thread;
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for (thread = 0; thread < NTHREADS; thread++) {
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if (events[thread] == 0)
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continue;
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total += get_set_bit_count64(events[thread]);
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}
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return total;
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}
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static uint32_t
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get_first_control_word(uint32_t flags, const uint64_t * events)
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{
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int thread, event;
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for (thread = 0; thread < NTHREADS; thread++) {
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if (events[thread] != 0)
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break;
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}
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if (thread == NTHREADS)
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return -1;
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event = find_first_set_bit64(events[thread]);
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return make_cp0_perf_control(flags, thread, event);
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}
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static uint32_t
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get_next_control_word(uint32_t current_control_word, const uint64_t * events)
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{
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int thread = cp0_perf_control_get_thread(current_control_word);
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int event = cp0_perf_control_get_event(current_control_word);
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int i;
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event = find_next_set_bit64(events[thread], event);
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for (i = 0; event == -1 && i < NTHREADS; i++) {
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thread = (thread + 1) % NTHREADS;
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if (events[thread] == 0)
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continue;
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event = find_first_set_bit64(events[thread]);
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}
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ASSERT(event != -1);
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return make_cp0_perf_control(current_control_word, thread, event);
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}
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/* Global state per core */
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#define MY_CORE_NUM (cpu_ltop_map[PCPU_GET(cpuid)]/NTHREADS)
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#define my_perf_area (&(xlr_shared_config_area[MY_CORE_NUM]))
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static int num_events_array[NCORES];
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static uint32_t saved_timestamp_array[NCORES];
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static struct perf_config_data saved_config_array[NCORES];
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static int cc_sample_array[NCORES];
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#define num_events (num_events_array[MY_CORE_NUM])
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#define saved_timestamp (saved_timestamp_array[MY_CORE_NUM])
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#define saved_config (saved_config_array[MY_CORE_NUM])
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#define cc_sample (cc_sample_array[MY_CORE_NUM])
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static void
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do_sample_cc_registers(struct sample_q *q, uint32_t mask)
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{
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unsigned long flags;
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DPRINT("Sample CC registers %x", mask);
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msgrng_flags_save(flags);
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if (mask & 0x00000001)
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put_sample(q, CC_SAMPLE + 0, read_cc_registers_0123(CC_REG0), 0);
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if (mask & 0x00000002)
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put_sample(q, CC_SAMPLE + 1, read_cc_registers_4567(CC_REG0), 0);
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if (mask & 0x00000004)
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put_sample(q, CC_SAMPLE + 2, read_cc_registers_0123(CC_REG1), 0);
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if (mask & 0x00000008)
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put_sample(q, CC_SAMPLE + 3, read_cc_registers_4567(CC_REG1), 0);
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if (mask & 0x00000010)
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put_sample(q, CC_SAMPLE + 4, read_cc_registers_0123(CC_REG2), 0);
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if (mask & 0x00000020)
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put_sample(q, CC_SAMPLE + 5, read_cc_registers_4567(CC_REG2), 0);
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if (mask & 0x00000040)
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put_sample(q, CC_SAMPLE + 6, read_cc_registers_0123(CC_REG3), 0);
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if (mask & 0x00000080)
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put_sample(q, CC_SAMPLE + 7, read_cc_registers_4567(CC_REG3), 0);
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if (mask & 0x00000100)
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put_sample(q, CC_SAMPLE + 8, read_cc_registers_0123(CC_REG4), 0);
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if (mask & 0x00000200)
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put_sample(q, CC_SAMPLE + 9, read_cc_registers_4567(CC_REG4), 0);
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if (mask & 0x00000400)
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put_sample(q, CC_SAMPLE + 10, read_cc_registers_0123(CC_REG5), 0);
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if (mask & 0x00000800)
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put_sample(q, CC_SAMPLE + 11, read_cc_registers_4567(CC_REG5), 0);
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if (mask & 0x00001000)
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put_sample(q, CC_SAMPLE + 12, read_cc_registers_0123(CC_REG6), 0);
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if (mask & 0x00002000)
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put_sample(q, CC_SAMPLE + 13, read_cc_registers_4567(CC_REG6), 0);
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if (mask & 0x00004000)
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put_sample(q, CC_SAMPLE + 14, read_cc_registers_0123(CC_REG7), 0);
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if (mask & 0x00008000)
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put_sample(q, CC_SAMPLE + 15, read_cc_registers_4567(CC_REG7), 0);
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if (mask & 0x00010000)
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put_sample(q, CC_SAMPLE + 16, read_cc_registers_0123(CC_REG8), 0);
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if (mask & 0x00020000)
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put_sample(q, CC_SAMPLE + 17, read_cc_registers_4567(CC_REG8), 0);
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if (mask & 0x00040000)
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put_sample(q, CC_SAMPLE + 18, read_cc_registers_0123(CC_REG9), 0);
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if (mask & 0x00080000)
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put_sample(q, CC_SAMPLE + 19, read_cc_registers_4567(CC_REG9), 0);
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if (mask & 0x00100000)
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put_sample(q, CC_SAMPLE + 20, read_cc_registers_0123(CC_REG10), 0);
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if (mask & 0x00200000)
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put_sample(q, CC_SAMPLE + 21, read_cc_registers_4567(CC_REG10), 0);
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if (mask & 0x00400000)
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put_sample(q, CC_SAMPLE + 22, read_cc_registers_0123(CC_REG11), 0);
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if (mask & 0x00800000)
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put_sample(q, CC_SAMPLE + 23, read_cc_registers_4567(CC_REG11), 0);
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if (mask & 0x01000000)
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put_sample(q, CC_SAMPLE + 24, read_cc_registers_0123(CC_REG12), 0);
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if (mask & 0x02000000)
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put_sample(q, CC_SAMPLE + 24, read_cc_registers_4567(CC_REG12), 0);
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if (mask & 0x04000000)
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put_sample(q, CC_SAMPLE + 26, read_cc_registers_0123(CC_REG13), 0);
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if (mask & 0x08000000)
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put_sample(q, CC_SAMPLE + 27, read_cc_registers_4567(CC_REG13), 0);
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if (mask & 0x10000000)
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put_sample(q, CC_SAMPLE + 28, read_cc_registers_0123(CC_REG14), 0);
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if (mask & 0x20000000)
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put_sample(q, CC_SAMPLE + 29, read_cc_registers_4567(CC_REG14), 0);
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if (mask & 0x40000000)
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put_sample(q, CC_SAMPLE + 30, read_cc_registers_0123(CC_REG15), 0);
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if (mask & 0x80000000)
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put_sample(q, CC_SAMPLE + 31, read_cc_registers_4567(CC_REG15), 0);
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msgrng_flags_restore(flags);
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}
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static void
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reconfigure(void)
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{
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uint32_t cntr_cntrl;
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saved_config = my_perf_area->perf_config;
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num_events = get_num_events(saved_config.events);
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cc_sample = saved_config.cc_sample_rate;
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DPRINT("%d - reconfigure num_events = %d, events = %llx,%llx,%llx,%llx\n",
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processor_id(), num_events, saved_config.events[0],
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saved_config.events[1], saved_config.events[2], saved_config.events[3]);
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if (num_events == 0)
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return;
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cntr_cntrl = get_first_control_word(saved_config.flags, saved_config.events);
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write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0, cntr_cntrl);
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write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0); /* reset count */
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if (num_events > 1) {
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cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events);
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write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1, cntr_cntrl);
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write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0); /* reset count */
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}
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saved_timestamp = read_pic_6_timer_count();
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}
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int xlr_perfmon_no_event_count = 0;
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int xlr_perfmon_sample_count;
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/* timer callback routine */
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void
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xlr_perfmon_sampler(void *dummy)
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{
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uint32_t current_ts;
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uint32_t cntr_cntrl = 0;
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/* xlr_ack_interrupt(XLR_PERFMON_IPI_VECTOR); */
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if (my_perf_area->perf_config.magic != PERFMON_ACTIVE_MAGIC)
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return;
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/*
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* If there has been a change in configuation, update the
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* configuration
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*/
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if (saved_config.generation != my_perf_area->perf_config.generation) {
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reconfigure();
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return;
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}
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/* credit counter samples if reqd */
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if (saved_config.cc_register_mask && --cc_sample == 0) {
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cc_sample = saved_config.cc_sample_rate;
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do_sample_cc_registers(&my_perf_area->sample_fifo,
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my_perf_area->perf_config.cc_register_mask);
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}
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if (num_events == 0) {
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xlr_perfmon_no_event_count++;
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return;
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}
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/* put samples in the queue */
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current_ts = read_pic_6_timer_count();
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cntr_cntrl = read_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0);
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put_sample(&my_perf_area->sample_fifo, make_cpu_tag(cntr_cntrl),
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read_c0_register(CP0_PERF_COUNTER, PERFCNTR0), current_ts - saved_timestamp);
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xlr_perfmon_sample_count++;
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write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0); /* reset count */
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if (num_events > 1) {
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cntr_cntrl = read_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1);
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put_sample(&my_perf_area->sample_fifo, make_cpu_tag(cntr_cntrl),
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read_c0_register(CP0_PERF_COUNTER, PERFCNTR1), current_ts - saved_timestamp);
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xlr_perfmon_sample_count++;
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write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0); /* reset count */
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if (num_events > 2) {
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/* multiplex events */
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cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events);
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write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0, cntr_cntrl);
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cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events);
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write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1, cntr_cntrl);
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}
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}
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saved_timestamp = read_pic_6_timer_count();
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}
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/*
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* Initializes time to gather CPU performance counters and credit counters
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*/
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void
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xlr_perfmon_init_cpu(void *dummy)
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{
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int processor = cpu_ltop_map[PCPU_GET(cpuid)];
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/* run on just one thread per core */
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if (processor % 4)
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return;
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DPRINT("%d : configure with %p", processor, my_perf_area);
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memset(my_perf_area, 0, sizeof(*my_perf_area));
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init_fifo(&my_perf_area->sample_fifo);
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my_perf_area->perf_config.magic = PERFMON_ENABLED_MAGIC;
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my_perf_area->perf_config.generation = PERFMON_INITIAL_GENERATION;
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DPRINT("%d : Initialize", processor);
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return;
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}
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