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204 lines
7.5 KiB
C
204 lines
7.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright(c) 2002-2011 Exar Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification are permitted provided the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Exar Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#ifndef VXGE_HAL_RING_H
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#define VXGE_HAL_RING_H
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__EXTERN_BEGIN_DECLS
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typedef u8 vxge_hal_ring_block_t[VXGE_OS_HOST_PAGE_SIZE];
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#define VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET (VXGE_OS_HOST_PAGE_SIZE-8)
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#define VXGE_HAL_RING_MEMBLOCK_IDX_OFFSET (VXGE_OS_HOST_PAGE_SIZE-16)
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/*
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* struct __hal_ring_rxd_priv_t - Receive descriptor HAL-private data.
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* @dma_addr: DMA (mapped) address of _this_ descriptor.
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* @dma_handle: DMA handle used to map the descriptor onto device.
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* @dma_offset: Descriptor's offset in the memory block. HAL allocates
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* descriptors in memory blocks of %VXGE_OS_HOST_PAGE_SIZE
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* bytes. Each memblock is contiguous DMA-able memory. Each
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* memblock contains 1 or more 4KB RxD blocks visible to the
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* X3100 hardware.
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* @dma_object: DMA address and handle of the memory block that contains
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* the descriptor. This member is used only in the "checked"
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* version of the HAL (to enforce certain assertions);
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* otherwise it gets compiled out.
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* @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
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* @db_bytes: Number of doorbell bytes to be posted for this Rxd. This includes
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* next RxD block pointers
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*
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* Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA
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* information associated with the descriptor. Note that ULD can ask HAL
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* to allocate additional per-descriptor space for its own (ULD-specific)
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* purposes.
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*/
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typedef struct __hal_ring_rxd_priv_t {
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dma_addr_t dma_addr;
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pci_dma_h dma_handle;
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ptrdiff_t dma_offset;
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#if defined(VXGE_DEBUG_ASSERT)
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vxge_hal_mempool_dma_t *dma_object;
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#endif
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#if defined(VXGE_OS_MEMORY_CHECK)
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u32 allocated;
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#endif
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u32 db_bytes;
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} __hal_ring_rxd_priv_t;
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/*
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* struct __hal_ring_t - Ring channel.
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* @channel: Channel "base" of this ring, the common part of all HAL
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* channels.
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* @mempool: Memory pool, the pool from which descriptors get allocated.
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* (See vxge_hal_mm.h).
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* @config: Ring configuration, part of device configuration
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* (see vxge_hal_device_config_t {}).
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* @ring_length: Length of the ring
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* @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
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* as per X3100 User Guide.
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* @indicate_max_pkts: Maximum number of packets processed within a single
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* interrupt. Can be used to limit the time spent inside hw interrupt.
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* @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per X3100 spec,
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* 1-buffer mode descriptor is 32 byte long, etc.
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* @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor
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* data (e.g., DMA handle for Solaris)
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* @per_rxd_space: Per rxd space requested by ULD
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* @rxds_per_block: Number of descriptors per hardware-defined RxD
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* block. Depends on the (1-, 3-, 5-) buffer mode.
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* @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal
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* usage. Not to confuse with @rxd_priv_size.
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* @rxd_mem_avail: Available RxD memory
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* @db_byte_count: Number of doorbell bytes to be posted
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* @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
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* Used in conjunction with @indicate_max_pkts.
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* @active_sw_lros: List of Software LRO sessions in progess
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* @active_sw_lro_count: Number of Software LRO sessions in progess
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* @free_sw_lros: List of Software LRO sessions free
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* @free_sw_lro_count: Number of Software LRO sessions free
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* @sw_lro_lock: LRO session lists' lock
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* @callback: Channel completion callback. HAL invokes the callback when there
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* are new completions on that channel. In many implementations
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* the @callback executes in the hw interrupt context.
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* @rxd_init: Channel's descriptor-initialize callback.
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* See vxge_hal_ring_rxd_init_f {}.
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* If not NULL, HAL invokes the callback when opening the ring.
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* @rxd_term: Channel's descriptor-terminate callback. If not NULL,
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* HAL invokes the callback when closing the corresponding channel.
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* See also vxge_hal_channel_rxd_term_f {}.
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* @stats: Statistics for ring
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* Ring channel.
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*
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* Note: The structure is cache line aligned to better utilize
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* CPU cache performance.
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*/
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typedef struct __hal_ring_t {
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__hal_channel_t channel;
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vxge_hal_mempool_t *mempool;
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vxge_hal_ring_config_t *config;
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u32 ring_length;
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u32 buffer_mode;
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u32 indicate_max_pkts;
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u32 rxd_size;
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u32 rxd_priv_size;
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u32 per_rxd_space;
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u32 rxds_per_block;
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u32 rxdblock_priv_size;
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u32 rxd_mem_avail;
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u32 db_byte_count;
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u32 cmpl_cnt;
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vxge_hal_ring_callback_f callback;
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vxge_hal_ring_rxd_init_f rxd_init;
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vxge_hal_ring_rxd_term_f rxd_term;
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vxge_hal_vpath_stats_sw_ring_info_t *stats;
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} __vxge_os_attr_cacheline_aligned __hal_ring_t;
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#define VXGE_HAL_RING_ULD_PRIV(ring, rxdh) \
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ring->channel.dtr_arr[ \
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((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].uld_priv
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#define VXGE_HAL_RING_HAL_PRIV(ring, rxdh) \
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((__hal_ring_rxd_priv_t *)(ring->channel.dtr_arr[ \
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((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].hal_priv))
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#define VXGE_HAL_RING_POST_DOORBELL(vph, ringh) \
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{ \
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if (((__hal_ring_t *)(ringh))->config->post_mode == \
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VXGE_HAL_RING_POST_MODE_DOORBELL) { \
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vxge_hal_ring_rxd_post_post_db(vph); \
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} \
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}
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#define VXGE_HAL_RING_RXD_INDEX(rxdp) \
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(u32)((vxge_hal_ring_rxd_5_t *)rxdp)->host_control
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/* ========================== RING PRIVATE API ============================ */
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u64
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__hal_ring_first_block_address_get(
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vxge_hal_ring_h ringh);
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vxge_hal_status_e
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__hal_ring_create(
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vxge_hal_vpath_h vpath_handle,
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vxge_hal_ring_attr_t *attr);
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void
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__hal_ring_abort(
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vxge_hal_ring_h ringh,
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vxge_hal_reopen_e reopen);
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vxge_hal_status_e
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__hal_ring_reset(
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vxge_hal_ring_h ringh);
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void
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__hal_ring_delete(
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vxge_hal_vpath_h vpath_handle);
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vxge_hal_status_e
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vxge_hal_ring_initial_replenish(
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__hal_ring_t *ring,
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vxge_hal_reopen_e reopen);
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vxge_hal_status_e
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__hal_ring_frame_length_set(
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__hal_virtualpath_t *vpath,
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u32 new_frmlen);
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__EXTERN_END_DECLS
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#endif /* VXGE_HAL_RING_H */
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