3a4d0022de
* Add some shifts that I'm using in userspace (athalq.) However, this exposes a fun little bug..
131 lines
5.2 KiB
C
131 lines
5.2 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2004 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_ATH_AR5210DESC_H
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#define _DEV_ATH_AR5210DESC_H
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/*
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* Defintions for the DMA descriptors used by the Atheros
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* AR5210/AR5211 and AR5110 Wireless Lan controller parts.
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*/
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/* DMA descriptors */
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struct ar5210_desc {
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uint32_t ds_link; /* link pointer */
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uint32_t ds_data; /* data buffer pointer */
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uint32_t ds_ctl0; /* DMA control 0 */
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uint32_t ds_ctl1; /* DMA control 1 */
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uint32_t ds_status0; /* DMA status 0 */
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uint32_t ds_status1; /* DMA status 1 */
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} __packed;
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#define AR5210DESC(_ds) ((struct ar5210_desc *)(_ds))
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#define AR5210DESC_CONST(_ds) ((const struct ar5210_desc *)(_ds))
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/* TX ds_ctl0 */
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#define AR_FrameLen 0x00000fff /* frame length */
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#define AR_HdrLen 0x0003f000 /* header length */
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#define AR_HdrLen_S 12
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#define AR_XmitRate 0x003c0000 /* txrate */
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#define AR_XmitRate_S 18
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#define AR_Rate_6M 0xb
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#define AR_Rate_9M 0xf
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#define AR_Rate_12M 0xa
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#define AR_Rate_18M 0xe
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#define AR_Rate_24M 0x9
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#define AR_Rate_36M 0xd
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#define AR_Rate_48M 0x8
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#define AR_Rate_54M 0xc
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#define AR_RTSCTSEnable 0x00400000 /* RTS/CTS enable */
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#define AR_LongPkt 0x00800000 /* long packet indication */
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#define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
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#define AR_AntModeXmit 0x02000000 /* TX antenna seslection */
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#define AR_FrmType 0x1c000000 /* frame type indication */
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#define AR_FrmType_S 26
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#define AR_Frm_Normal 0x00000000 /* normal frame */
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#define AR_Frm_ATIM 0x04000000 /* ATIM frame */
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#define AR_Frm_PSPOLL 0x08000000 /* PS poll frame */
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#define AR_Frm_NoDelay 0x0c000000 /* no delay data */
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#define AR_Frm_PIFS 0x10000000 /* PIFS data */
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#define AR_TxInterReq 0x20000000 /* TX interrupt request */
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#define AR_EncryptKeyValid 0x40000000 /* EncryptKeyIdx is valid */
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/* TX ds_ctl1 */
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#define AR_BufLen 0x00000fff /* data buffer length */
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#define AR_More 0x00001000 /* more desc in this frame */
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#define AR_EncryptKeyIdx 0x0007e000 /* ecnrypt key table index */
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#define AR_EncryptKeyIdx_S 13
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#define AR_RTSDuration 0xfff80000 /* lower 13bit of duration */
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#define AR_RTSDuration_S 19
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/* RX ds_ctl1 */
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/* AR_BufLen 0x00000fff data buffer length */
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#define AR_RxInterReq 0x00002000 /* RX interrupt request */
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/* TX ds_status0 */
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#define AR_FrmXmitOK 0x00000001 /* TX success */
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#define AR_ExcessiveRetries 0x00000002 /* excessive retries */
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#define AR_FIFOUnderrun 0x00000004 /* TX FIFO underrun */
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#define AR_Filtered 0x00000008 /* TX filter indication */
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/* NB: the spec has the Short+Long retry counts reversed */
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#define AR_LongRetryCnt 0x000000f0 /* long retry count */
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#define AR_LongRetryCnt_S 4
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#define AR_ShortRetryCnt 0x00000f00 /* short retry count */
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#define AR_ShortRetryCnt_S 8
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#define AR_SendTimestamp 0xffff0000 /* TX timestamp */
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#define AR_SendTimestamp_S 16
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/* RX ds_status0 */
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#define AR_DataLen 0x00000fff /* RX data length */
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/* AR_More 0x00001000 more desc in this frame */
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#define AR_RcvAntenna 0x00004000 /* received on ant 1 */
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#define AR_RcvRate 0x00078000 /* reception rate */
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#define AR_RcvRate_S 15
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#define AR_RcvSigStrength 0x07f80000 /* receive signal strength */
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#define AR_RcvSigStrength_S 19
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/* TX ds_status1 */
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#define AR_Done 0x00000001 /* descripter complete */
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#define AR_SeqNum 0x00001ffe /* TX sequence number */
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#define AR_AckSigStrength 0x001fe000 /* strength of ACK */
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#define AR_AckSigStrength_S 13
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/* RX ds_status1 */
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/* AR_Done 0x00000001 descripter complete */
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#define AR_FrmRcvOK 0x00000002 /* frame reception success */
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#define AR_CRCErr 0x00000004 /* CRC error */
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#define AR_FIFOOverrun 0x00000008 /* RX FIFO overrun */
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#define AR_DecryptCRCErr 0x00000010 /* Decryption CRC fiailure */
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#define AR_PHYErr 0x000000e0 /* PHY error */
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#define AR_PHYErr_S 5
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#define AR_PHYErr_NoErr 0x00000000 /* No error */
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#define AR_PHYErr_Tim 0x00000020 /* Timing error */
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#define AR_PHYErr_Par 0x00000040 /* Parity error */
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#define AR_PHYErr_Rate 0x00000060 /* Illegal rate */
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#define AR_PHYErr_Len 0x00000080 /* Illegal length */
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#define AR_PHYErr_QAM 0x000000a0 /* 64 QAM rate */
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#define AR_PHYErr_Srv 0x000000c0 /* Service bit error */
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#define AR_PHYErr_TOR 0x000000e0 /* Transmit override receive */
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#define AR_KeyIdxValid 0x00000100 /* decryption key index valid */
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#define AR_KeyIdx 0x00007e00 /* Decryption key index */
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#define AR_KeyIdx_S 9
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#define AR_RcvTimestamp 0x0fff8000 /* timestamp */
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#define AR_RcvTimestamp_S 15
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#define AR_KeyCacheMiss 0x10000000 /* key cache miss indication */
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#endif /* _DEV_ATH_AR5210DESC_H_ */
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