c21e84e4db
o Configure controller to use dynamic TBD as TSO requires that operation mode. o Add a dummy TBD to tx_cb_u as TSO can access one more TBD in TSO operation. o Increase a DMA segment size to 4096 to hold a full IP segment with link layer header. o Unlike other TSO capable controllers, 82550/82551 does not modify the first IP packet in TSO operation so driver should create an IP packet with proper header. Subsequent IP packets are generated from the header information in the first IP packet header. Likewise pseudo checksum also should be computed by driver for the first packet. o TSO requires one more TBD to hold total TCP payload. To make code simple for TSO/non-TSO case, increase the index of the first available TBD array. o Remove KASSERT that checks the size of a DMA segment should be less than or equal to MCLBYTES as it's no longer valid in TSO. o Tx threshold and number of TBDs field is used to store MSS in TSO. So don't set the Tx threshold in TSO case.
212 lines
7.6 KiB
C
212 lines
7.6 KiB
C
/*-
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
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* Ethernet driver
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*/
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/*
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* Number of transmit control blocks. This determines the number
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* of transmit buffers that can be chained in the CB list.
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* This must be a power of two.
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*/
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#define FXP_NTXCB 128
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#define FXP_NTXCB_HIWAT ((FXP_NTXCB * 7) / 10)
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/*
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* Maximum size of a DMA segment.
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*/
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#define FXP_TSO_SEGSIZE 4096
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/*
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* Size of the TxCB list.
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*/
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#define FXP_TXCB_SZ (FXP_NTXCB * sizeof(struct fxp_cb_tx))
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/*
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* Macro to obtain the DMA address of a virtual address in the
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* TxCB list based on the base DMA address of the TxCB list.
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*/
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#define FXP_TXCB_DMA_ADDR(sc, addr) \
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(sc->fxp_desc.cbl_addr + (uintptr_t)addr - \
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(uintptr_t)sc->fxp_desc.cbl_list)
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/*
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* Number of completed TX commands at which point an interrupt
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* will be generated to garbage collect the attached buffers.
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* Must be at least one less than FXP_NTXCB, and should be
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* enough less so that the transmitter doesn't becomes idle
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* during the buffer rundown (which would reduce performance).
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*/
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#define FXP_CXINT_THRESH 120
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/*
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* TxCB list index mask. This is used to do list wrap-around.
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*/
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#define FXP_TXCB_MASK (FXP_NTXCB - 1)
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/*
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* Number of receive frame area buffers. These are large so chose
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* wisely.
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*/
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#ifdef DEVICE_POLLING
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#define FXP_NRFABUFS 192
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#else
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#define FXP_NRFABUFS 64
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#endif
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/*
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* Maximum number of seconds that the receiver can be idle before we
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* assume it's dead and attempt to reset it by reprogramming the
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* multicast filter. This is part of a work-around for a bug in the
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* NIC. See fxp_stats_update().
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*/
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#define FXP_MAX_RX_IDLE 15
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/*
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* Default maximum time, in microseconds, that an interrupt may be delayed
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* in an attempt to coalesce interrupts. This is only effective if the Intel
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* microcode is loaded, and may be changed via either loader tunables or
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* sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h.
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*/
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#define TUNABLE_INT_DELAY 1000
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/*
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* Default number of packets that will be bundled, before an interrupt is
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* generated. This is only effective if the Intel microcode is loaded, and
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* may be changed via either loader tunables or sysctl. This may not be
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* present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD
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* entry in rcvbundl.h.
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*/
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#define TUNABLE_BUNDLE_MAX 6
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#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define FXP_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
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/*
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* Structures to handle TX and RX descriptors.
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*/
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struct fxp_rx {
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struct fxp_rx *rx_next;
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struct mbuf *rx_mbuf;
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bus_dmamap_t rx_map;
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uint32_t rx_addr;
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};
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struct fxp_tx {
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struct fxp_tx *tx_next;
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struct fxp_cb_tx *tx_cb;
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struct mbuf *tx_mbuf;
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bus_dmamap_t tx_map;
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};
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struct fxp_desc_list {
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struct fxp_rx rx_list[FXP_NRFABUFS];
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struct fxp_tx tx_list[FXP_NTXCB];
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struct fxp_tx mcs_tx;
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struct fxp_rx *rx_head;
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struct fxp_rx *rx_tail;
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struct fxp_tx *tx_first;
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struct fxp_tx *tx_last;
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struct fxp_rfa *rfa_list;
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struct fxp_cb_tx *cbl_list;
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uint32_t cbl_addr;
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bus_dma_tag_t rx_tag;
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};
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/*
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* NOTE: Elements are ordered for optimal cacheline behavior, and NOT
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* for functional grouping.
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*/
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struct fxp_softc {
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struct ifnet *ifp; /* per-interface network data */
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struct resource *fxp_res[2]; /* I/O and IRQ resources */
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struct resource_spec *fxp_spec; /* the resource spec we used */
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void *ih; /* interrupt handler cookie */
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struct mtx sc_mtx;
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bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */
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bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */
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bus_dmamap_t fxp_smap; /* bus DMA map for stats */
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bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */
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bus_dmamap_t cbl_map; /* DMA map for the TxCB list */
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bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */
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bus_dmamap_t mcs_map; /* DMA map for the multicast setup */
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bus_dmamap_t spare_map; /* spare DMA map */
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struct fxp_desc_list fxp_desc; /* descriptors management struct */
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int maxtxseg; /* maximum # of TX segments */
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int maxsegsize; /* maximum size of a TX segment */
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int tx_queued; /* # of active TxCB's */
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int need_mcsetup; /* multicast filter needs programming */
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struct fxp_stats *fxp_stats; /* Pointer to interface stats */
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uint32_t stats_addr; /* DMA address of the stats structure */
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int rx_idle_secs; /* # of seconds RX has been idle */
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struct callout stat_ch; /* stat callout */
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int watchdog_timer; /* seconds until chip reset */
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struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */
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uint32_t mcs_addr; /* DMA address of the multicast cmd */
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struct ifmedia sc_media; /* media information */
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device_t miibus;
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device_t dev;
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int tunable_int_delay; /* interrupt delay value for ucode */
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int tunable_bundle_max; /* max # frames per interrupt (ucode) */
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int tunable_noflow; /* flow control disabled */
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int rnr; /* RNR events */
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int eeprom_size; /* size of serial EEPROM */
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int suspended; /* 0 = normal 1 = suspended or dead */
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int cu_resume_bug;
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int revision;
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int flags;
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uint8_t rfa_size;
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uint32_t tx_cmd;
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};
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#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */
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#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */
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#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */
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#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */
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#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */
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#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */
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#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */
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#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */
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#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */
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#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */
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#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */
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#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */
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#define FXP_FLAG_82559_RXCSUM 0x1000 /* 82559 compatible RX checksum */
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/* Macros to ease CSR access. */
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#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg)
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#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)
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#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)
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#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)
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#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val)
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#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val)
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