b8aa843c63
- Split core DRM routines back into their own module, rather than using the nasty templated system like before. - Development-class R300 support in radeon driver (requires userland pieces, of course). - Mach64 driver (haven't tested in a while -- my mach64s no longer fit in the testbox). Covers Rage Pros, Rage Mobility P/M, Rage XL, and some others. - i915 driver files, which just need to get drm_drv.c fixed to allow attachment to the drmsub device. Covers i830 through i915 integrated graphics. - savage driver files, which should require minimal changes to work. Covers the Savage3D, Savage IX/MX, Savage 4, ProSavage. - Support for color and texture tiling and HyperZ features of Radeon. Thanks to: scottl (much p4 handholding) Jung-uk Kim (helpful prodding) PR: [1] kern/76879, [2] kern/72548 Submitted by: [1] Alex, lesha at intercaf dot ru [2] Shaun Jurrens, shaun at shamz dot net
748 lines
19 KiB
C
748 lines
19 KiB
C
/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
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* Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com */
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/*-
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Rickard E. (Rik) Faith <faith@valinux.com>
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* Jeff Hartmann <jhartmann@valinux.com>
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* Keith Whitwell <keith@tungstengraphics.com>
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*
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* Rewritten by:
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* Gareth Hughes <gareth@valinux.com>
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*
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* $FreeBSD$
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*/
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#include "dev/drm/drmP.h"
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#include "dev/drm/drm.h"
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#include "dev/drm/mga_drm.h"
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#include "dev/drm/mga_drv.h"
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#define MGA_DEFAULT_USEC_TIMEOUT 10000
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#define MGA_FREELIST_DEBUG 0
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static int mga_do_cleanup_dma(drm_device_t * dev);
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/* ================================================================
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* Engine control
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*/
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int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
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{
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u32 status = 0;
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int i;
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DRM_DEBUG("\n");
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for (i = 0; i < dev_priv->usec_timeout; i++) {
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status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
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if (status == MGA_ENDPRDMASTS) {
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MGA_WRITE8(MGA_CRTC_INDEX, 0);
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return 0;
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}
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DRM_UDELAY(1);
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}
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#if MGA_DMA_DEBUG
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DRM_ERROR("failed!\n");
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DRM_INFO(" status=0x%08x\n", status);
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#endif
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return DRM_ERR(EBUSY);
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}
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static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
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{
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drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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DRM_DEBUG("\n");
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/* The primary DMA stream should look like new right about now.
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*/
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primary->tail = 0;
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primary->space = primary->size;
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primary->last_flush = 0;
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sarea_priv->last_wrap = 0;
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/* FIXME: Reset counters, buffer ages etc...
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*/
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/* FIXME: What else do we need to reinitialize? WARP stuff?
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*/
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return 0;
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}
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/* ================================================================
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* Primary DMA stream
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*/
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void mga_do_dma_flush(drm_mga_private_t * dev_priv)
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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u32 head, tail;
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u32 status = 0;
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int i;
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DMA_LOCALS;
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DRM_DEBUG("\n");
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/* We need to wait so that we can do an safe flush */
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for (i = 0; i < dev_priv->usec_timeout; i++) {
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status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
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if (status == MGA_ENDPRDMASTS)
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break;
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DRM_UDELAY(1);
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}
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if (primary->tail == primary->last_flush) {
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DRM_DEBUG(" bailing out...\n");
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return;
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}
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tail = primary->tail + dev_priv->primary->offset;
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/* We need to pad the stream between flushes, as the card
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* actually (partially?) reads the first of these commands.
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* See page 4-16 in the G400 manual, middle of the page or so.
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*/
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BEGIN_DMA(1);
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DMA_BLOCK(MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
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ADVANCE_DMA();
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primary->last_flush = primary->tail;
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head = MGA_READ(MGA_PRIMADDRESS);
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if (head <= tail) {
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primary->space = primary->size - primary->tail;
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} else {
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primary->space = head - tail;
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}
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DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
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DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset);
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DRM_DEBUG(" space = 0x%06x\n", primary->space);
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mga_flush_write_combine();
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MGA_WRITE(MGA_PRIMEND, tail | MGA_PAGPXFER);
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DRM_DEBUG("done.\n");
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}
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void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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u32 head, tail;
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DMA_LOCALS;
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DRM_DEBUG("\n");
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BEGIN_DMA_WRAP();
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DMA_BLOCK(MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
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ADVANCE_DMA();
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tail = primary->tail + dev_priv->primary->offset;
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primary->tail = 0;
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primary->last_flush = 0;
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primary->last_wrap++;
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head = MGA_READ(MGA_PRIMADDRESS);
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if (head == dev_priv->primary->offset) {
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primary->space = primary->size;
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} else {
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primary->space = head - dev_priv->primary->offset;
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}
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DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
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DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
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DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
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DRM_DEBUG(" space = 0x%06x\n", primary->space);
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mga_flush_write_combine();
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MGA_WRITE(MGA_PRIMEND, tail | MGA_PAGPXFER);
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set_bit(0, &primary->wrapped);
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DRM_DEBUG("done.\n");
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}
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void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
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u32 head = dev_priv->primary->offset;
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DRM_DEBUG("\n");
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sarea_priv->last_wrap++;
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DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
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mga_flush_write_combine();
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MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
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clear_bit(0, &primary->wrapped);
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DRM_DEBUG("done.\n");
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}
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/* ================================================================
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* Freelist management
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*/
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#define MGA_BUFFER_USED ~0
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#define MGA_BUFFER_FREE 0
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#if MGA_FREELIST_DEBUG
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static void mga_freelist_print(drm_device_t * dev)
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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drm_mga_freelist_t *entry;
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DRM_INFO("\n");
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DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
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dev_priv->sarea_priv->last_dispatch,
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(unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
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dev_priv->primary->offset));
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DRM_INFO("current freelist:\n");
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for (entry = dev_priv->head->next; entry; entry = entry->next) {
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DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
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entry, entry->buf->idx, entry->age.head,
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entry->age.head - dev_priv->primary->offset);
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}
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DRM_INFO("\n");
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}
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#endif
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static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv)
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{
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drm_device_dma_t *dma = dev->dma;
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drm_buf_t *buf;
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drm_mga_buf_priv_t *buf_priv;
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drm_mga_freelist_t *entry;
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int i;
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DRM_DEBUG("count=%d\n", dma->buf_count);
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dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
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if (dev_priv->head == NULL)
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return DRM_ERR(ENOMEM);
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memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
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SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
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for (i = 0; i < dma->buf_count; i++) {
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buf = dma->buflist[i];
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buf_priv = buf->dev_private;
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entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
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if (entry == NULL)
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return DRM_ERR(ENOMEM);
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memset(entry, 0, sizeof(drm_mga_freelist_t));
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entry->next = dev_priv->head->next;
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entry->prev = dev_priv->head;
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SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
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entry->buf = buf;
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if (dev_priv->head->next != NULL)
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dev_priv->head->next->prev = entry;
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if (entry->next == NULL)
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dev_priv->tail = entry;
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buf_priv->list_entry = entry;
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buf_priv->discard = 0;
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buf_priv->dispatched = 0;
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dev_priv->head->next = entry;
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}
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return 0;
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}
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static void mga_freelist_cleanup(drm_device_t * dev)
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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drm_mga_freelist_t *entry;
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drm_mga_freelist_t *next;
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DRM_DEBUG("\n");
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entry = dev_priv->head;
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while (entry) {
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next = entry->next;
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drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
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entry = next;
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}
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dev_priv->head = dev_priv->tail = NULL;
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}
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#if 0
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/* FIXME: Still needed?
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*/
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static void mga_freelist_reset(drm_device_t * dev)
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{
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drm_device_dma_t *dma = dev->dma;
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drm_buf_t *buf;
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drm_mga_buf_priv_t *buf_priv;
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int i;
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for (i = 0; i < dma->buf_count; i++) {
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buf = dma->buflist[i];
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buf_priv = buf->dev_private;
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SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
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}
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}
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#endif
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static drm_buf_t *mga_freelist_get(drm_device_t * dev)
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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drm_mga_freelist_t *next;
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drm_mga_freelist_t *prev;
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drm_mga_freelist_t *tail = dev_priv->tail;
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u32 head, wrap;
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DRM_DEBUG("\n");
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head = MGA_READ(MGA_PRIMADDRESS);
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wrap = dev_priv->sarea_priv->last_wrap;
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DRM_DEBUG(" tail=0x%06lx %d\n",
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tail->age.head ?
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tail->age.head - dev_priv->primary->offset : 0,
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tail->age.wrap);
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DRM_DEBUG(" head=0x%06lx %d\n",
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head - dev_priv->primary->offset, wrap);
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if (TEST_AGE(&tail->age, head, wrap)) {
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prev = dev_priv->tail->prev;
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next = dev_priv->tail;
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prev->next = NULL;
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next->prev = next->next = NULL;
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dev_priv->tail = prev;
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SET_AGE(&next->age, MGA_BUFFER_USED, 0);
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return next->buf;
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}
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DRM_DEBUG("returning NULL!\n");
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return NULL;
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}
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int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf)
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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drm_mga_buf_priv_t *buf_priv = buf->dev_private;
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drm_mga_freelist_t *head, *entry, *prev;
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DRM_DEBUG("age=0x%06lx wrap=%d\n",
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buf_priv->list_entry->age.head -
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dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
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entry = buf_priv->list_entry;
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head = dev_priv->head;
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if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
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SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
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prev = dev_priv->tail;
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prev->next = entry;
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entry->prev = prev;
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entry->next = NULL;
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} else {
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prev = head->next;
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head->next = entry;
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prev->prev = entry;
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entry->prev = head;
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entry->next = prev;
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}
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return 0;
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}
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/* ================================================================
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* DMA initialization, cleanup
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*/
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static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init)
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{
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drm_mga_private_t *dev_priv;
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int ret;
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DRM_DEBUG("\n");
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dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
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if (!dev_priv)
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return DRM_ERR(ENOMEM);
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memset(dev_priv, 0, sizeof(drm_mga_private_t));
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dev_priv->chipset = init->chipset;
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dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
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if (init->sgram) {
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dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
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} else {
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dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
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}
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dev_priv->maccess = init->maccess;
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dev_priv->fb_cpp = init->fb_cpp;
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dev_priv->front_offset = init->front_offset;
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dev_priv->front_pitch = init->front_pitch;
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dev_priv->back_offset = init->back_offset;
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dev_priv->back_pitch = init->back_pitch;
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dev_priv->depth_cpp = init->depth_cpp;
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dev_priv->depth_offset = init->depth_offset;
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dev_priv->depth_pitch = init->depth_pitch;
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/* FIXME: Need to support AGP textures...
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*/
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dev_priv->texture_offset = init->texture_offset[0];
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dev_priv->texture_size = init->texture_size[0];
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DRM_GETSAREA();
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if (!dev_priv->sarea) {
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DRM_ERROR("failed to find sarea!\n");
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/* Assign dev_private so we can do cleanup. */
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dev->dev_private = (void *)dev_priv;
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mga_do_cleanup_dma(dev);
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return DRM_ERR(EINVAL);
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}
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dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
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if (!dev_priv->mmio) {
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DRM_ERROR("failed to find mmio region!\n");
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/* Assign dev_private so we can do cleanup. */
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dev->dev_private = (void *)dev_priv;
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mga_do_cleanup_dma(dev);
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return DRM_ERR(EINVAL);
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}
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dev_priv->status = drm_core_findmap(dev, init->status_offset);
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if (!dev_priv->status) {
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DRM_ERROR("failed to find status page!\n");
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/* Assign dev_private so we can do cleanup. */
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dev->dev_private = (void *)dev_priv;
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mga_do_cleanup_dma(dev);
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return DRM_ERR(EINVAL);
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}
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dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
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if (!dev_priv->warp) {
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DRM_ERROR("failed to find warp microcode region!\n");
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/* Assign dev_private so we can do cleanup. */
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dev->dev_private = (void *)dev_priv;
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mga_do_cleanup_dma(dev);
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return DRM_ERR(EINVAL);
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}
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dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
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if (!dev_priv->primary) {
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DRM_ERROR("failed to find primary dma region!\n");
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/* Assign dev_private so we can do cleanup. */
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dev->dev_private = (void *)dev_priv;
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mga_do_cleanup_dma(dev);
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return DRM_ERR(EINVAL);
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}
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dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
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if (!dev->agp_buffer_map) {
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DRM_ERROR("failed to find dma buffer region!\n");
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/* Assign dev_private so we can do cleanup. */
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dev->dev_private = (void *)dev_priv;
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mga_do_cleanup_dma(dev);
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return DRM_ERR(EINVAL);
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}
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|
|
|
dev_priv->sarea_priv =
|
|
(drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
|
|
init->sarea_priv_offset);
|
|
|
|
drm_core_ioremap(dev_priv->warp, dev);
|
|
drm_core_ioremap(dev_priv->primary, dev);
|
|
drm_core_ioremap(dev->agp_buffer_map, dev);
|
|
|
|
if (!dev_priv->warp->handle ||
|
|
!dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
|
|
DRM_ERROR("failed to ioremap agp regions!\n");
|
|
/* Assign dev_private so we can do cleanup. */
|
|
dev->dev_private = (void *)dev_priv;
|
|
mga_do_cleanup_dma(dev);
|
|
return DRM_ERR(ENOMEM);
|
|
}
|
|
|
|
ret = mga_warp_install_microcode(dev_priv);
|
|
if (ret < 0) {
|
|
DRM_ERROR("failed to install WARP ucode!\n");
|
|
/* Assign dev_private so we can do cleanup. */
|
|
dev->dev_private = (void *)dev_priv;
|
|
mga_do_cleanup_dma(dev);
|
|
return ret;
|
|
}
|
|
|
|
ret = mga_warp_init(dev_priv);
|
|
if (ret < 0) {
|
|
DRM_ERROR("failed to init WARP engine!\n");
|
|
/* Assign dev_private so we can do cleanup. */
|
|
dev->dev_private = (void *)dev_priv;
|
|
mga_do_cleanup_dma(dev);
|
|
return ret;
|
|
}
|
|
|
|
dev_priv->prim.status = (u32 *) dev_priv->status->handle;
|
|
|
|
mga_do_wait_for_idle(dev_priv);
|
|
|
|
/* Init the primary DMA registers.
|
|
*/
|
|
MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
|
|
#if 0
|
|
MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
|
|
MGA_PRIMPTREN1); /* DWGSYNC */
|
|
#endif
|
|
|
|
dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
|
|
dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
|
|
+ dev_priv->primary->size);
|
|
dev_priv->prim.size = dev_priv->primary->size;
|
|
|
|
dev_priv->prim.tail = 0;
|
|
dev_priv->prim.space = dev_priv->prim.size;
|
|
dev_priv->prim.wrapped = 0;
|
|
|
|
dev_priv->prim.last_flush = 0;
|
|
dev_priv->prim.last_wrap = 0;
|
|
|
|
dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
|
|
|
|
dev_priv->prim.status[0] = dev_priv->primary->offset;
|
|
dev_priv->prim.status[1] = 0;
|
|
|
|
dev_priv->sarea_priv->last_wrap = 0;
|
|
dev_priv->sarea_priv->last_frame.head = 0;
|
|
dev_priv->sarea_priv->last_frame.wrap = 0;
|
|
|
|
if (mga_freelist_init(dev, dev_priv) < 0) {
|
|
DRM_ERROR("could not initialize freelist\n");
|
|
/* Assign dev_private so we can do cleanup. */
|
|
dev->dev_private = (void *)dev_priv;
|
|
mga_do_cleanup_dma(dev);
|
|
return DRM_ERR(ENOMEM);
|
|
}
|
|
|
|
/* Make dev_private visable to others. */
|
|
dev->dev_private = (void *)dev_priv;
|
|
return 0;
|
|
}
|
|
|
|
static int mga_do_cleanup_dma(drm_device_t * dev)
|
|
{
|
|
DRM_DEBUG("\n");
|
|
|
|
/* Make sure interrupts are disabled here because the uninstall ioctl
|
|
* may not have been called from userspace and after dev_private
|
|
* is freed, it's too late.
|
|
*/
|
|
if (dev->irq_enabled)
|
|
drm_irq_uninstall(dev);
|
|
|
|
if (dev->dev_private) {
|
|
drm_mga_private_t *dev_priv = dev->dev_private;
|
|
|
|
if (dev_priv->warp != NULL)
|
|
drm_core_ioremapfree(dev_priv->warp, dev);
|
|
if (dev_priv->primary != NULL)
|
|
drm_core_ioremapfree(dev_priv->primary, dev);
|
|
if (dev->agp_buffer_map != NULL) {
|
|
drm_core_ioremapfree(dev->agp_buffer_map, dev);
|
|
dev->agp_buffer_map = NULL;
|
|
}
|
|
|
|
if (dev_priv->head != NULL) {
|
|
mga_freelist_cleanup(dev);
|
|
}
|
|
|
|
drm_free(dev->dev_private, sizeof(drm_mga_private_t),
|
|
DRM_MEM_DRIVER);
|
|
dev->dev_private = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mga_dma_init(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_mga_init_t init;
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data,
|
|
sizeof(init));
|
|
|
|
switch (init.func) {
|
|
case MGA_INIT_DMA:
|
|
return mga_do_init_dma(dev, &init);
|
|
case MGA_CLEANUP_DMA:
|
|
return mga_do_cleanup_dma(dev);
|
|
}
|
|
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
/* ================================================================
|
|
* Primary DMA stream management
|
|
*/
|
|
|
|
int mga_dma_flush(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
|
|
drm_lock_t lock;
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data,
|
|
sizeof(lock));
|
|
|
|
DRM_DEBUG("%s%s%s\n",
|
|
(lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
|
|
(lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
|
|
(lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
|
|
|
|
WRAP_WAIT_WITH_RETURN(dev_priv);
|
|
|
|
if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
|
|
mga_do_dma_flush(dev_priv);
|
|
}
|
|
|
|
if (lock.flags & _DRM_LOCK_QUIESCENT) {
|
|
#if MGA_DMA_DEBUG
|
|
int ret = mga_do_wait_for_idle(dev_priv);
|
|
if (ret < 0)
|
|
DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
|
|
return ret;
|
|
#else
|
|
return mga_do_wait_for_idle(dev_priv);
|
|
#endif
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int mga_dma_reset(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
return mga_do_dma_reset(dev_priv);
|
|
}
|
|
|
|
/* ================================================================
|
|
* DMA buffer management
|
|
*/
|
|
|
|
static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
|
|
{
|
|
drm_buf_t *buf;
|
|
int i;
|
|
|
|
for (i = d->granted_count; i < d->request_count; i++) {
|
|
buf = mga_freelist_get(dev);
|
|
if (!buf)
|
|
return DRM_ERR(EAGAIN);
|
|
|
|
buf->filp = filp;
|
|
|
|
if (DRM_COPY_TO_USER(&d->request_indices[i],
|
|
&buf->idx, sizeof(buf->idx)))
|
|
return DRM_ERR(EFAULT);
|
|
if (DRM_COPY_TO_USER(&d->request_sizes[i],
|
|
&buf->total, sizeof(buf->total)))
|
|
return DRM_ERR(EFAULT);
|
|
|
|
d->granted_count++;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int mga_dma_buffers(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_device_dma_t *dma = dev->dma;
|
|
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
|
|
drm_dma_t __user *argp = (void __user *)data;
|
|
drm_dma_t d;
|
|
int ret = 0;
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
|
|
|
|
/* Please don't send us buffers.
|
|
*/
|
|
if (d.send_count != 0) {
|
|
DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
|
|
DRM_CURRENTPID, d.send_count);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
/* We'll send you buffers.
|
|
*/
|
|
if (d.request_count < 0 || d.request_count > dma->buf_count) {
|
|
DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
|
|
DRM_CURRENTPID, d.request_count, dma->buf_count);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
WRAP_TEST_WITH_RETURN(dev_priv);
|
|
|
|
d.granted_count = 0;
|
|
|
|
if (d.request_count) {
|
|
ret = mga_dma_get_buffers(filp, dev, &d);
|
|
}
|
|
|
|
DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
|
|
|
|
return ret;
|
|
}
|
|
|
|
void mga_driver_pretakedown(drm_device_t * dev)
|
|
{
|
|
mga_do_cleanup_dma(dev);
|
|
}
|
|
|
|
int mga_driver_dma_quiescent(drm_device_t * dev)
|
|
{
|
|
drm_mga_private_t *dev_priv = dev->dev_private;
|
|
return mga_do_wait_for_idle(dev_priv);
|
|
}
|