a66dc0c52b
have ACLE support built in. The ACLE (ARM C Language Extensions) defines a set of standardized symbols which indicate the architecture version and features available. ACLE support is built in to modern compilers (both clang and gcc), but absent from gcc prior to 4.4. ARM (the company) provides the acle-compat.h header file to define the right symbols for older versions of gcc. Basically, acle-compat.h does for arm about the same thing cdefs.h does for freebsd: defines standardized macros that work no matter which compiler you use. If ARM hadn't provided this file we would have ended up with a big #ifdef __arm__ section in cdefs.h with our own compatibility shims. Remove #include <machine/acle-compat.h> from the zillion other places (an ever-growing list) that it appears. Since style(9) requires sys/types.h or sys/param.h early in the include list, and both of those lead to including cdefs.h, only a couple special cases still need to include acle-compat.h directly. Loves it: imp
187 lines
4.7 KiB
C
187 lines
4.7 KiB
C
/*-
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* Copyright 2016 Svatopluk Kraus <skra@FreeBSD.org>
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* Copyright 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef MACHINE_CPU_V4_H
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#define MACHINE_CPU_V4_H
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/* There are no user serviceable parts here, they may change without notice */
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#ifndef _KERNEL
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#error Only include this file in the kernel
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#endif
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#include <machine/atomic.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuinfo.h>
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#include <machine/sysreg.h>
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#if __ARM_ARCH >= 6
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#error Never include this file for ARMv6
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#else
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#define CPU_ASID_KERNEL 0
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/*
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* Macros to generate CP15 (system control processor) read/write functions.
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*/
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#define _FX(s...) #s
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#define _RF0(fname, aname...) \
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static __inline register_t \
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fname(void) \
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{ \
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register_t reg; \
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__asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \
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return(reg); \
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}
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#define _R64F0(fname, aname) \
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static __inline uint64_t \
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fname(void) \
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{ \
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uint64_t reg; \
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__asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \
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return(reg); \
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}
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#define _WF0(fname, aname...) \
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static __inline void \
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fname(void) \
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{ \
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__asm __volatile("mcr\t" _FX(aname)); \
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}
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#define _WF1(fname, aname...) \
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static __inline void \
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fname(register_t reg) \
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{ \
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__asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \
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}
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/*
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* Publicly accessible functions
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*/
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/* Various control registers */
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_RF0(cp15_cpacr_get, CP15_CPACR(%0))
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_WF1(cp15_cpacr_set, CP15_CPACR(%0))
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_RF0(cp15_dfsr_get, CP15_DFSR(%0))
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_RF0(cp15_ttbr_get, CP15_TTBR0(%0))
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_RF0(cp15_dfar_get, CP15_DFAR(%0))
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/* XScale */
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_RF0(cp15_actlr_get, CP15_ACTLR(%0))
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_WF1(cp15_actlr_set, CP15_ACTLR(%0))
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/*CPU id registers */
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_RF0(cp15_midr_get, CP15_MIDR(%0))
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_RF0(cp15_ctr_get, CP15_CTR(%0))
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_RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
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_RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
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_RF0(cp15_sctlr_get, CP15_SCTLR(%0))
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#undef _FX
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#undef _RF0
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#undef _WF0
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#undef _WF1
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/*
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* armv4/5 compatibility shims.
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*
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* These functions provide armv4 cache maintenance using the new armv6 names.
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* Included here are just the functions actually used now in common code; it may
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* be necessary to add things here over time.
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*
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* The callers of the dcache functions expect these routines to handle address
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* and size values which are not aligned to cacheline boundaries; the armv4 and
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* armv5 asm code handles that.
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*/
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static __inline void
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tlb_flush_all(void)
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{
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cpu_tlb_flushID();
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cpu_cpwait();
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}
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static __inline void
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icache_sync(vm_offset_t va, vm_size_t size)
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{
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cpu_icache_sync_range(va, size);
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}
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static __inline void
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dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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{
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cpu_dcache_inv_range(va, size);
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#ifdef ARM_L2_PIPT
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cpu_l2cache_inv_range(pa, size);
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#else
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cpu_l2cache_inv_range(va, size);
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#endif
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}
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static __inline void
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dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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{
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/* See armv6 code, above, for why we do L2 before L1 in this case. */
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#ifdef ARM_L2_PIPT
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cpu_l2cache_inv_range(pa, size);
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#else
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cpu_l2cache_inv_range(va, size);
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#endif
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cpu_dcache_inv_range(va, size);
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}
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static __inline void
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dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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{
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cpu_dcache_wb_range(va, size);
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#ifdef ARM_L2_PIPT
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cpu_l2cache_wb_range(pa, size);
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#else
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cpu_l2cache_wb_range(va, size);
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#endif
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}
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static __inline void
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dcache_wbinv_poc_all(void)
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{
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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}
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#endif /* _KERNEL */
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#endif /* MACHINE_CPU_V4_H */
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