3a5d5a69ce
allocator for jumbo frame. Also remove unneeded jlist lock which is no longer required to protect jumbo buffers. With these changes jumbo frame performance of nfe(4) was slightly increased and users should not encounter jumbo buffer allocation failure anymore.
314 lines
9.6 KiB
C
314 lines
9.6 KiB
C
/* $OpenBSD: if_nfereg.h,v 1.16 2006/02/22 19:23:44 damien Exp $ */
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/*-
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* Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#define NFE_RX_RING_COUNT 256
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#define NFE_JUMBO_RX_RING_COUNT NFE_RX_RING_COUNT
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#define NFE_TX_RING_COUNT 256
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#define NFE_PROC_DEFAULT ((NFE_RX_RING_COUNT * 3) / 4)
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#define NFE_PROC_MIN 50
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#define NFE_PROC_MAX (NFE_RX_RING_COUNT - 1)
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#define NFE_INC(x, y) (x) = ((x) + 1) % y
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/* RX/TX MAC addr + type + VLAN + align + slack */
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#define NFE_RX_HEADERS 64
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/* Maximum MTU size. */
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#define NV_PKTLIMIT_1 ETH_DATA_LEN /* Hard limit not known. */
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#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia:9202 */
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#define NFE_JUMBO_FRAMELEN NV_PKTLIMIT_2
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#define NFE_JUMBO_MTU \
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(NFE_JUMBO_FRAMELEN - NFE_RX_HEADERS)
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#define NFE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
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#define NFE_MAX_SCATTER 32
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#define NFE_TSO_MAXSGSIZE 4096
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#define NFE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
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#define NFE_IRQ_STATUS 0x000
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#define NFE_IRQ_MASK 0x004
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#define NFE_SETUP_R6 0x008
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#define NFE_IMTIMER 0x00c
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#define NFE_MSI_MAP0 0x020
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#define NFE_MSI_MAP1 0x024
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#define NFE_MSI_IRQ_MASK 0x030
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#define NFE_MAC_RESET 0x03c
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#define NFE_MISC1 0x080
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#define NFE_TX_CTL 0x084
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#define NFE_TX_STATUS 0x088
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#define NFE_RXFILTER 0x08c
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#define NFE_RXBUFSZ 0x090
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#define NFE_RX_CTL 0x094
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#define NFE_RX_STATUS 0x098
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#define NFE_RNDSEED 0x09c
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#define NFE_SETUP_R1 0x0a0
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#define NFE_SETUP_R2 0x0a4
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#define NFE_MACADDR_HI 0x0a8
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#define NFE_MACADDR_LO 0x0ac
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#define NFE_MULTIADDR_HI 0x0b0
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#define NFE_MULTIADDR_LO 0x0b4
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#define NFE_MULTIMASK_HI 0x0b8
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#define NFE_MULTIMASK_LO 0x0bc
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#define NFE_PHY_IFACE 0x0c0
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#define NFE_TX_RING_ADDR_LO 0x100
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#define NFE_RX_RING_ADDR_LO 0x104
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#define NFE_RING_SIZE 0x108
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#define NFE_TX_UNK 0x10c
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#define NFE_LINKSPEED 0x110
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#define NFE_SETUP_R5 0x130
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#define NFE_SETUP_R3 0x13C
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#define NFE_SETUP_R7 0x140
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#define NFE_RXTX_CTL 0x144
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#define NFE_TX_RING_ADDR_HI 0x148
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#define NFE_RX_RING_ADDR_HI 0x14c
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#define NFE_TX_PAUSE_FRAME 0x170
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#define NFE_PHY_STATUS 0x180
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#define NFE_SETUP_R4 0x184
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#define NFE_STATUS 0x188
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#define NFE_PHY_SPEED 0x18c
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#define NFE_PHY_CTL 0x190
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#define NFE_PHY_DATA 0x194
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#define NFE_WOL_CTL 0x200
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#define NFE_PATTERN_CRC 0x204
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#define NFE_PATTERN_MASK 0x208
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#define NFE_PWR_CAP 0x268
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#define NFE_PWR_STATE 0x26c
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#define NFE_VTAG_CTL 0x300
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#define NFE_MSIX_MAP0 0x3e0
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#define NFE_MSIX_MAP1 0x3e4
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#define NFE_MSIX_IRQ_STATUS 0x3f0
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#define NFE_PWR2_CTL 0x600
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#define NFE_MAC_RESET_MAGIC 0x00f3
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#define NFE_MAC_ADDR_INORDER 0x8000
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#define NFE_PHY_ERROR 0x00001
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#define NFE_PHY_WRITE 0x00400
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#define NFE_PHY_BUSY 0x08000
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#define NFE_PHYADD_SHIFT 5
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#define NFE_STATUS_MAGIC 0x140000
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#define NFE_R1_MAGIC_1000 0x14050f
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#define NFE_R1_MAGIC_10_100 0x16070f
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#define NFE_R1_MAGIC_DEFAULT 0x15050f
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#define NFE_R2_MAGIC 0x16
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#define NFE_R4_MAGIC 0x08
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#define NFE_R6_MAGIC 0x03
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#define NFE_WOL_MAGIC 0x1111
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#define NFE_RX_START 0x01
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#define NFE_TX_START 0x01
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#define NFE_IRQ_RXERR 0x0001
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#define NFE_IRQ_RX 0x0002
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#define NFE_IRQ_RX_NOBUF 0x0004
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#define NFE_IRQ_TXERR 0x0008
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#define NFE_IRQ_TX_DONE 0x0010
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#define NFE_IRQ_TIMER 0x0020
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#define NFE_IRQ_LINK 0x0040
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#define NFE_IRQ_TXERR2 0x0080
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#define NFE_IRQ_TX1 0x0100
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#define NFE_IRQ_WANTED \
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(NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \
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NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \
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NFE_IRQ_LINK)
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#define NFE_RXTX_KICKTX 0x0001
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#define NFE_RXTX_BIT1 0x0002
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#define NFE_RXTX_BIT2 0x0004
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#define NFE_RXTX_RESET 0x0010
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#define NFE_RXTX_VTAG_STRIP 0x0040
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#define NFE_RXTX_VTAG_INSERT 0x0080
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#define NFE_RXTX_RXCSUM 0x0400
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#define NFE_RXTX_V2MAGIC 0x2100
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#define NFE_RXTX_V3MAGIC 0x2200
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#define NFE_RXFILTER_MAGIC 0x007f0000
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#define NFE_PFF_RX_PAUSE (1 << 3)
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#define NFE_PFF_LOOPBACK (1 << 4)
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#define NFE_PFF_U2M (1 << 5)
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#define NFE_PFF_PROMISC (1 << 7)
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#define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
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/* default interrupt moderation timer of 128us */
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#define NFE_IM_DEFAULT ((128 * 100) / 1024)
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#define NFE_VTAG_ENABLE (1 << 13)
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#define NFE_PWR_VALID (1 << 8)
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#define NFE_PWR_WAKEUP (1 << 15)
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#define NFE_PWR2_WAKEUP_MASK 0x0f11
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#define NFE_PWR2_REVA3 (1 << 0)
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#define NFE_MEDIA_SET 0x10000
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#define NFE_MEDIA_1000T 0x00032
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#define NFE_MEDIA_100TX 0x00064
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#define NFE_MEDIA_10T 0x003e8
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#define NFE_PHY_100TX (1 << 0)
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#define NFE_PHY_1000T (1 << 1)
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#define NFE_PHY_HDX (1 << 8)
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#define NFE_MISC1_MAGIC 0x003b0f3c
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#define NFE_MISC1_TX_PAUSE (1 << 0)
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#define NFE_MISC1_HDX (1 << 1)
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#define NFE_TX_PAUSE_FRAME_DISABLE 0x1ff0080
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#define NFE_TX_PAUSE_FRAME_ENABLE 0x0c00030
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#define NFE_SEED_MASK 0x0003ff00
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#define NFE_SEED_10T 0x00007f00
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#define NFE_SEED_100TX 0x00002d00
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#define NFE_SEED_1000T 0x00007400
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#define NFE_MSI_MESSAGES 8
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#define NFE_MSI_VECTOR_0_ENABLED 0x01
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/*
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* It seems that nForce supports only the lower 40 bits of a DMA address.
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*/
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#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
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#define NFE_DMA_MAXADDR BUS_SPACE_MAXADDR
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#else
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#define NFE_DMA_MAXADDR 0xFFFFFFFFFF
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#endif
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#define NFE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
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#define NFE_ADDR_HI(x) ((u_int64_t) (x) >> 32)
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/* Rx/Tx descriptor */
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struct nfe_desc32 {
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uint32_t physaddr;
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uint16_t length;
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uint16_t flags;
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#define NFE_RX_FIXME_V1 0x6004
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#define NFE_RX_VALID_V1 (1 << 0)
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#define NFE_TX_ERROR_V1 0x7808
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#define NFE_TX_LASTFRAG_V1 (1 << 0)
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#define NFE_RX_ERROR1_V1 (1<<7)
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#define NFE_RX_ERROR2_V1 (1<<8)
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#define NFE_RX_ERROR3_V1 (1<<9)
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#define NFE_RX_ERROR4_V1 (1<<10)
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} __packed;
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#define NFE_V1_TXERR "\020" \
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"\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \
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"\08FORCEDINT\03RETRY\00LASTPACKET"
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/* V2 Rx/Tx descriptor */
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struct nfe_desc64 {
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uint32_t physaddr[2];
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uint32_t vtag;
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#define NFE_RX_VTAG (1 << 16)
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#define NFE_TX_VTAG (1 << 18)
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uint16_t length;
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uint16_t flags;
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#define NFE_RX_FIXME_V2 0x4300
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#define NFE_RX_VALID_V2 (1 << 13)
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#define NFE_TX_ERROR_V2 0x5c04
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#define NFE_TX_LASTFRAG_V2 (1 << 13)
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#define NFE_RX_ERROR1_V2 (1<<2)
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#define NFE_RX_ERROR2_V2 (1<<3)
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#define NFE_RX_ERROR3_V2 (1<<4)
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#define NFE_RX_ERROR4_V2 (1<<5)
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} __packed;
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#define NFE_V2_TXERR "\020" \
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"\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
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#define NFE_RING_ALIGN (sizeof(struct nfe_desc64))
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/* flags common to V1/V2 descriptors */
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#define NFE_RX_UDP_CSUMOK (1 << 10)
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#define NFE_RX_TCP_CSUMOK (1 << 11)
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#define NFE_RX_IP_CSUMOK (1 << 12)
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#define NFE_RX_ERROR (1 << 14)
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#define NFE_RX_READY (1 << 15)
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#define NFE_RX_LEN_MASK 0x3fff
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#define NFE_TX_TCP_UDP_CSUM (1 << 10)
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#define NFE_TX_IP_CSUM (1 << 11)
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#define NFE_TX_TSO (1 << 12)
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#define NFE_TX_TSO_SHIFT 14
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#define NFE_TX_VALID (1 << 15)
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#define NFE_READ(sc, reg) \
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bus_read_4((sc)->nfe_res[0], (reg))
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#define NFE_WRITE(sc, reg, val) \
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bus_write_4((sc)->nfe_res[0], (reg), (val))
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#define NFE_TIMEOUT 1000
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#ifndef PCI_VENDOR_NVIDIA
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#define PCI_VENDOR_NVIDIA 0x10DE
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#endif
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#define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3
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#define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6
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#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086
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#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C
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#define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF
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#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056
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#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057
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#define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037
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#define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038
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#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268
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#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269
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#define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372
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#define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373
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#define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5
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#define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6
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#define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee
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#define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453
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#define PCI_PRODUCT_NVIDIA_MCP67_LAN1 0x054c
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#define PCI_PRODUCT_NVIDIA_MCP67_LAN2 0x054d
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#define PCI_PRODUCT_NVIDIA_MCP67_LAN3 0x054e
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#define PCI_PRODUCT_NVIDIA_MCP67_LAN4 0x054f
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN
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#define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1
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#define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2
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#define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1
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#define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2
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#define NFE_DEBUG 0x0000
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#define NFE_DEBUG_INIT 0x0001
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#define NFE_DEBUG_RUNNING 0x0002
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#define NFE_DEBUG_DEINIT 0x0004
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#define NFE_DEBUG_IOCTL 0x0008
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#define NFE_DEBUG_INTERRUPT 0x0010
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#define NFE_DEBUG_API 0x0020
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#define NFE_DEBUG_LOCK 0x0040
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#define NFE_DEBUG_BROKEN 0x0080
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#define NFE_DEBUG_MII 0x0100
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#define NFE_DEBUG_ALL 0xFFFF
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