7113afc84c
This patch has the driver for 10Gigabit Ethernet controller in AMD SoC. This driver is written compatible to the Iflib framework. The existing driver is for the old version of hardware. The submitted driver here is for the recent versions of the hardware where the Ethernet controller is PCI-E based. Submitted by: Rajesh Kumar <rajesh1.kumar@amd.com> MFC after: 1 month Relnotes: yes Differential Revision: https://reviews.freebsd.org/D25793
348 lines
14 KiB
C
348 lines
14 KiB
C
/*
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* AMD 10Gb Ethernet driver
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*
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* Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
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*
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* This file is available to you under your choice of the following two
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* licenses:
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*
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* License 1: GPLv2
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*
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* This file is free software; you may copy, redistribute and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or (at
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* your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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* Inc. unless otherwise expressly agreed to in writing between Synopsys
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* and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for Licensed
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* Product with Synopsys or any supplement thereto. Permission is hereby
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* granted, free of charge, to any person obtaining a copy of this software
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* annotated with this license and the Software, to deal in the Software
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* without restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* License 2: Modified BSD
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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* Inc. unless otherwise expressly agreed to in writing between Synopsys
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* and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for Licensed
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* Product with Synopsys or any supplement thereto. Permission is hereby
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* granted, free of charge, to any person obtaining a copy of this software
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* annotated with this license and the Software, to deal in the Software
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* without restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "xgbe.h"
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#include "xgbe-common.h"
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int
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xgbe_calc_rx_buf_size(struct ifnet *netdev, unsigned int mtu)
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{
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unsigned int rx_buf_size;
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if (mtu > XGMAC_JUMBO_PACKET_MTU)
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return (-EINVAL);
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rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
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rx_buf_size = min(max(rx_buf_size, XGBE_RX_MIN_BUF_SIZE), PAGE_SIZE);
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rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
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~(XGBE_RX_BUF_ALIGN - 1);
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return (rx_buf_size);
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}
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void
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xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
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{
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unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
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struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
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DBGPR("-->xgbe_get_all_hw_features\n");
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mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
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mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
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mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
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memset(hw_feat, 0, sizeof(*hw_feat));
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hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
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/* Hardware feature register 0 */
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hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
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hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
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hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
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hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
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hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
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hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
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hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
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hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
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hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
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hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
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hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
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hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
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ADDMACADRSEL);
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hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
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hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
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hw_feat->vxn = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
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/* Hardware feature register 1 */
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hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
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RXFIFOSIZE);
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hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
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TXFIFOSIZE);
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hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
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hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
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hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
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hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
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hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
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hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
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hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
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hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
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hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
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HASHTBLSZ);
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hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
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L3L4FNUM);
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/* Hardware feature register 2 */
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hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
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hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
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hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
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hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
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hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
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hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
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/* Translate the Hash Table size into actual number */
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switch (hw_feat->hash_table_size) {
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case 0:
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break;
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case 1:
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hw_feat->hash_table_size = 64;
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break;
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case 2:
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hw_feat->hash_table_size = 128;
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break;
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case 3:
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hw_feat->hash_table_size = 256;
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break;
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}
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/* Translate the address width setting into actual number */
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switch (hw_feat->dma_width) {
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case 0:
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hw_feat->dma_width = 32;
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break;
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case 1:
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hw_feat->dma_width = 40;
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break;
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case 2:
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hw_feat->dma_width = 48;
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break;
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default:
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hw_feat->dma_width = 32;
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}
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/* The Queue, Channel and TC counts are zero based so increment them
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* to get the actual number
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*/
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hw_feat->rx_q_cnt++;
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hw_feat->tx_q_cnt++;
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hw_feat->rx_ch_cnt++;
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hw_feat->tx_ch_cnt++;
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hw_feat->tc_cnt++;
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/* Translate the fifo sizes into actual numbers */
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hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
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hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
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DBGPR("%s: Tx fifo 0x%x Rx fifo 0x%x\n", __func__,
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hw_feat->tx_fifo_size, hw_feat->rx_fifo_size);
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DBGPR("Hardware features:\n");
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/* Hardware feature register 0 */
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DBGPR(" 1GbE support : %s\n",
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hw_feat->gmii ? "yes" : "no");
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DBGPR(" VLAN hash filter : %s\n",
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hw_feat->vlhash ? "yes" : "no");
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DBGPR(" MDIO interface : %s\n",
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hw_feat->sma ? "yes" : "no");
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DBGPR(" Wake-up packet support : %s\n",
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hw_feat->rwk ? "yes" : "no");
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DBGPR(" Magic packet support : %s\n",
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hw_feat->mgk ? "yes" : "no");
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DBGPR(" Management counters : %s\n",
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hw_feat->mmc ? "yes" : "no");
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DBGPR(" ARP offload : %s\n",
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hw_feat->aoe ? "yes" : "no");
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DBGPR(" IEEE 1588-2008 Timestamp : %s\n",
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hw_feat->ts ? "yes" : "no");
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DBGPR(" Energy Efficient Ethernet : %s\n",
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hw_feat->eee ? "yes" : "no");
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DBGPR(" TX checksum offload : %s\n",
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hw_feat->tx_coe ? "yes" : "no");
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DBGPR(" RX checksum offload : %s\n",
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hw_feat->rx_coe ? "yes" : "no");
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DBGPR(" Additional MAC addresses : %u\n",
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hw_feat->addn_mac);
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DBGPR(" Timestamp source : %s\n",
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(hw_feat->ts_src == 1) ? "internal" :
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(hw_feat->ts_src == 2) ? "external" :
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(hw_feat->ts_src == 3) ? "internal/external" : "n/a");
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DBGPR(" SA/VLAN insertion : %s\n",
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hw_feat->sa_vlan_ins ? "yes" : "no");
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/* Hardware feature register 1 */
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DBGPR(" RX fifo size : %u\n",
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hw_feat->rx_fifo_size);
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DBGPR(" TX fifo size : %u\n",
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hw_feat->tx_fifo_size);
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DBGPR(" IEEE 1588 high word : %s\n",
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hw_feat->adv_ts_hi ? "yes" : "no");
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DBGPR(" DMA width : %u\n",
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hw_feat->dma_width);
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DBGPR(" Data Center Bridging : %s\n",
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hw_feat->dcb ? "yes" : "no");
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DBGPR(" Split header : %s\n",
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hw_feat->sph ? "yes" : "no");
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DBGPR(" TCP Segmentation Offload : %s\n",
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hw_feat->tso ? "yes" : "no");
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DBGPR(" Debug memory interface : %s\n",
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hw_feat->dma_debug ? "yes" : "no");
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DBGPR(" Receive Side Scaling : %s\n",
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hw_feat->rss ? "yes" : "no");
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DBGPR(" Traffic Class count : %u\n",
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hw_feat->tc_cnt);
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DBGPR(" Hash table size : %u\n",
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hw_feat->hash_table_size);
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DBGPR(" L3/L4 Filters : %u\n",
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hw_feat->l3l4_filter_num);
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/* Hardware feature register 2 */
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DBGPR(" RX queue count : %u\n",
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hw_feat->rx_q_cnt);
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DBGPR(" TX queue count : %u\n",
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hw_feat->tx_q_cnt);
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DBGPR(" RX DMA channel count : %u\n",
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hw_feat->rx_ch_cnt);
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DBGPR(" TX DMA channel count : %u\n",
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hw_feat->rx_ch_cnt);
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DBGPR(" PPS outputs : %u\n",
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hw_feat->pps_out_num);
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DBGPR(" Auxiliary snapshot inputs : %u\n",
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hw_feat->aux_snap_num);
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DBGPR("<--xgbe_get_all_hw_features\n");
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}
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void
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xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
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{
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struct xgbe_hw_if *hw_if = &pdata->hw_if;
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DBGPR("-->xgbe_init_tx_coalesce\n");
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pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
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pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
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hw_if->config_tx_coalesce(pdata);
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DBGPR("<--xgbe_init_tx_coalesce\n");
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}
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void
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xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
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{
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struct xgbe_hw_if *hw_if = &pdata->hw_if;
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DBGPR("-->xgbe_init_rx_coalesce\n");
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pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
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pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
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pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
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hw_if->config_rx_coalesce(pdata);
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DBGPR("<--xgbe_init_rx_coalesce\n");
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}
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