1e7af4cc7a
RockChip PLL have two modes controlled by a register, a "slow mode" (the default one) where the frequency is derived from the 24Mhz oscillator on the board, and a "normal" one when the pll take it's input from the real PLL output. Default the mode to normal for all the PLLs.
284 lines
7.2 KiB
C
284 lines
7.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <arm64/rockchip/clk/rk_clk_pll.h>
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#include "clkdev_if.h"
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struct rk_clk_pll_sc {
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uint32_t base_offset;
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uint32_t gate_offset;
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uint32_t gate_shift;
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uint32_t mode_reg;
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uint32_t mode_val;
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uint32_t flags;
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struct rk_clk_pll_rate *rates;
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struct rk_clk_pll_rate *frac_rates;
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};
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#define WRITE4(_clk, off, val) \
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CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
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#define READ4(_clk, off, val) \
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CLKDEV_READ_4(clknode_get_device(_clk), off, val)
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#define DEVICE_LOCK(_clk) \
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CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
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#define DEVICE_UNLOCK(_clk) \
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
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#define RK_CLK_PLL_FBDIV_OFFSET 0
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#define RK_CLK_PLL_FBDIV_SHIFT 0
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#define RK_CLK_PLL_FBDIV_MASK 0xFFF
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#define RK_CLK_PLL_POSTDIV1_OFFSET 0
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#define RK_CLK_PLL_POSTDIV1_SHIFT 12
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#define RK_CLK_PLL_POSTDIV1_MASK 0x7000
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#define RK_CLK_PLL_DSMPD_OFFSET 4
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#define RK_CLK_PLL_DSMPD_SHIFT 12
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#define RK_CLK_PLL_DSMPD_MASK 0x1000
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#define RK_CLK_PLL_REFDIV_OFFSET 4
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#define RK_CLK_PLL_REFDIV_SHIFT 0
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#define RK_CLK_PLL_REFDIV_MASK 0x3F
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#define RK_CLK_PLL_POSTDIV2_OFFSET 4
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#define RK_CLK_PLL_POSTDIV2_SHIFT 6
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#define RK_CLK_PLL_POSTDIV2_MASK 0x1C0
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#define RK_CLK_PLL_FRAC_OFFSET 8
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#define RK_CLK_PLL_FRAC_SHIFT 0
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#define RK_CLK_PLL_FRAC_MASK 0xFFFFFF
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#define RK_CLK_PLL_LOCK_MASK 0x400
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#define RK_CLK_PLL_WRITE_MASK 0xFFFF0000
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static int
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rk_clk_pll_init(struct clknode *clk, device_t dev)
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{
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struct rk_clk_pll_sc *sc;
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sc = clknode_get_softc(clk);
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static int
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rk_clk_pll_set_gate(struct clknode *clk, bool enable)
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{
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struct rk_clk_pll_sc *sc;
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uint32_t val;
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sc = clknode_get_softc(clk);
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if ((sc->flags & RK_CLK_PLL_HAVE_GATE) == 0)
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return (0);
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DEVICE_LOCK(clk);
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READ4(clk, sc->gate_offset, &val);
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if (enable)
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val &= ~(1 << sc->gate_shift);
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else
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val |= 1 << sc->gate_shift;
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WRITE4(clk, sc->gate_offset, val | RK_CLK_PLL_MASK);
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DEVICE_UNLOCK(clk);
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return (0);
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}
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static int
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rk_clk_pll_recalc(struct clknode *clk, uint64_t *freq)
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{
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struct rk_clk_pll_sc *sc;
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uint64_t rate;
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uint32_t dsmpd, refdiv, fbdiv;
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uint32_t postdiv1, postdiv2, frac;
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uint32_t raw1, raw2, raw3;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(clk);
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READ4(clk, sc->base_offset, &raw1);
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READ4(clk, sc->base_offset + 4, &raw2);
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READ4(clk, sc->base_offset + 8, &raw3);
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fbdiv = (raw1 & RK_CLK_PLL_FBDIV_MASK) >> RK_CLK_PLL_FBDIV_SHIFT;
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postdiv1 = (raw1 & RK_CLK_PLL_POSTDIV1_MASK) >> RK_CLK_PLL_POSTDIV1_SHIFT;
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dsmpd = (raw2 & RK_CLK_PLL_DSMPD_MASK) >> RK_CLK_PLL_DSMPD_SHIFT;
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refdiv = (raw2 & RK_CLK_PLL_REFDIV_MASK) >> RK_CLK_PLL_REFDIV_SHIFT;
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postdiv2 = (raw2 & RK_CLK_PLL_POSTDIV2_MASK) >> RK_CLK_PLL_POSTDIV2_SHIFT;
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frac = (raw3 & RK_CLK_PLL_FRAC_MASK) >> RK_CLK_PLL_FRAC_SHIFT;
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DEVICE_UNLOCK(clk);
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rate = *freq * fbdiv / refdiv;
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if (dsmpd == 0) {
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/* Fractional mode */
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uint64_t frac_rate;
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frac_rate = *freq * frac / refdiv;
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rate += frac_rate >> 24;
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}
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*freq = rate / postdiv1 / postdiv2;
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if (*freq % 2)
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*freq = *freq + 1;
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return (0);
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}
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static int
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rk_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
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int flags, int *stop)
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{
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struct rk_clk_pll_rate *rates;
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struct rk_clk_pll_sc *sc;
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uint32_t reg;
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int timeout;
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sc = clknode_get_softc(clk);
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if (sc->rates)
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rates = sc->rates;
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else if (sc->frac_rates)
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rates = sc->frac_rates;
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else
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return (EINVAL);
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for (; rates->freq; rates++) {
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if (rates->freq == *fout)
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break;
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}
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if (rates->freq == 0) {
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*stop = 1;
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return (EINVAL);
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}
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DEVICE_LOCK(clk);
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/* Setting postdiv1 and fbdiv */
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READ4(clk, sc->base_offset, ®);
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reg &= ~(RK_CLK_PLL_POSTDIV1_MASK | RK_CLK_PLL_FBDIV_MASK);
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reg |= rates->postdiv1 << RK_CLK_PLL_POSTDIV1_SHIFT;
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reg |= rates->fbdiv << RK_CLK_PLL_FBDIV_SHIFT;
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WRITE4(clk, sc->base_offset, reg | RK_CLK_PLL_WRITE_MASK);
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/* Setting dsmpd, postdiv2 and refdiv */
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READ4(clk, sc->base_offset + 0x4, ®);
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reg &= ~(RK_CLK_PLL_DSMPD_MASK | RK_CLK_PLL_POSTDIV2_MASK |
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RK_CLK_PLL_REFDIV_MASK);
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reg |= rates->dsmpd << RK_CLK_PLL_DSMPD_SHIFT;
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reg |= rates->postdiv2 << RK_CLK_PLL_POSTDIV2_SHIFT;
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reg |= rates->refdiv << RK_CLK_PLL_REFDIV_SHIFT;
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WRITE4(clk, sc->base_offset + 0x4, reg | RK_CLK_PLL_WRITE_MASK);
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/* Setting frac */
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READ4(clk, sc->base_offset + 0x8, ®);
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reg &= ~RK_CLK_PLL_FRAC_MASK;
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reg |= rates->frac << RK_CLK_PLL_FRAC_SHIFT;
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WRITE4(clk, sc->base_offset + 0x8, reg);
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/* Setting to normal mode */
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READ4(clk, sc->mode_reg, ®);
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reg |= sc->mode_val << 16 | sc->mode_val;
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WRITE4(clk, sc->mode_reg, reg);
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/* Reading lock */
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for (timeout = 1000; timeout; timeout--) {
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READ4(clk, sc->base_offset + 0x4, ®);
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if ((reg & RK_CLK_PLL_LOCK_MASK) == 0)
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break;
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DELAY(1);
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}
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DEVICE_UNLOCK(clk);
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*stop = 1;
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return (0);
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}
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static clknode_method_t rk_clk_pll_clknode_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, rk_clk_pll_init),
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CLKNODEMETHOD(clknode_set_gate, rk_clk_pll_set_gate),
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CLKNODEMETHOD(clknode_recalc_freq, rk_clk_pll_recalc),
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CLKNODEMETHOD(clknode_set_freq, rk_clk_pll_set_freq),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(rk_clk_pll_clknode, rk_clk_pll_clknode_class,
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rk_clk_pll_clknode_methods, sizeof(struct rk_clk_pll_sc), clknode_class);
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int
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rk_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef)
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{
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struct clknode *clk;
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struct rk_clk_pll_sc *sc;
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clk = clknode_create(clkdom, &rk_clk_pll_clknode_class,
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&clkdef->clkdef);
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if (clk == NULL)
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return (1);
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sc = clknode_get_softc(clk);
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sc->base_offset = clkdef->base_offset;
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sc->gate_offset = clkdef->gate_offset;
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sc->gate_shift = clkdef->gate_shift;
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sc->mode_reg = clkdef->mode_reg;
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sc->mode_val = clkdef->mode_val;
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sc->flags = clkdef->flags;
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sc->rates = clkdef->rates;
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sc->frac_rates = clkdef->frac_rates;
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clknode_register(clkdom, clk);
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return (0);
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}
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