3df266dff9
The core clock (armclk) on RockChip SoC is special. It can derive it's clock from many PLLs but RockChip recommand to do it from "apll" on old SoC and "npll" on new SoC. The reason for choosing npll is that it's have less jitter and is more close to the arm core on the SoC. r333314 added the core clock as a composite clock but due to it's specials property we need to deal with it differently. A new rk_clk_armclk type is added for this and it supports only the "npll" as we don't run on old RockChip SoC that only have the "apll". It will always reparent to "npll" and set the frequency according to a rate table that is known to be good. For now we set the "npll" to the desired frequency and just set the core clk divider to 1 as its parent it just used for the core clk.
277 lines
6.5 KiB
C
277 lines
6.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* RockChip Clock and Reset Unit
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_gate.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <arm64/rockchip/clk/rk_clk_composite.h>
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#include <arm64/rockchip/clk/rk_clk_gate.h>
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#include <arm64/rockchip/clk/rk_clk_mux.h>
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#include <arm64/rockchip/clk/rk_clk_pll.h>
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#include <arm64/rockchip/clk/rk_cru.h>
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#include "clkdev_if.h"
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#include "hwreset_if.h"
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static struct resource_spec rk_cru_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg))
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#define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
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void rk3328_cru_register_clocks(struct rk_cru_softc *sc);
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static int
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rk_cru_write_4(device_t dev, bus_addr_t addr, uint32_t val)
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{
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struct rk_cru_softc *sc;
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sc = device_get_softc(dev);
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CCU_WRITE4(sc, addr, val);
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return (0);
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}
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static int
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rk_cru_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
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{
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struct rk_cru_softc *sc;
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sc = device_get_softc(dev);
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*val = CCU_READ4(sc, addr);
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return (0);
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}
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static int
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rk_cru_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
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{
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struct rk_cru_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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reg = CCU_READ4(sc, addr);
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reg &= ~clr;
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reg |= set;
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CCU_WRITE4(sc, addr, reg);
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return (0);
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}
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static int
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rk_cru_reset_assert(device_t dev, intptr_t id, bool reset)
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{
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struct rk_cru_softc *sc;
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uint32_t val;
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sc = device_get_softc(dev);
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if (id >= sc->nresets || sc->resets[id].offset == 0)
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return (0);
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mtx_lock(&sc->mtx);
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val = CCU_READ4(sc, sc->resets[id].offset);
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if (reset)
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val &= ~(1 << sc->resets[id].shift);
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else
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val |= 1 << sc->resets[id].shift;
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CCU_WRITE4(sc, sc->resets[id].offset, val);
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mtx_unlock(&sc->mtx);
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return (0);
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}
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static int
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rk_cru_reset_is_asserted(device_t dev, intptr_t id, bool *reset)
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{
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struct rk_cru_softc *sc;
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uint32_t val;
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sc = device_get_softc(dev);
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if (id >= sc->nresets || sc->resets[id].offset == 0)
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return (0);
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mtx_lock(&sc->mtx);
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val = CCU_READ4(sc, sc->resets[id].offset);
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*reset = (val & (1 << sc->resets[id].shift)) != 0 ? false : true;
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mtx_unlock(&sc->mtx);
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return (0);
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}
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static void
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rk_cru_device_lock(device_t dev)
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{
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struct rk_cru_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mtx);
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}
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static void
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rk_cru_device_unlock(device_t dev)
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{
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struct rk_cru_softc *sc;
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sc = device_get_softc(dev);
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mtx_unlock(&sc->mtx);
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}
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static int
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rk_cru_register_gates(struct rk_cru_softc *sc)
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{
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struct rk_clk_gate_def def;
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int i;
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for (i = 0; i < sc->ngates; i++) {
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if (sc->gates[i].name == NULL)
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continue;
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memset(&def, 0, sizeof(def));
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def.clkdef.id = sc->gates[i].id;
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def.clkdef.name = sc->gates[i].name;
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def.clkdef.parent_names = &sc->gates[i].parent_name;
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def.clkdef.parent_cnt = 1;
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def.offset = sc->gates[i].offset;
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def.shift = sc->gates[i].shift;
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def.mask = 1;
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def.on_value = 0;
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def.off_value = 1;
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rk_clk_gate_register(sc->clkdom, &def);
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}
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return (0);
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}
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int
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rk_cru_attach(device_t dev)
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{
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struct rk_cru_softc *sc;
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phandle_t node;
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int i;
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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if (bus_alloc_resources(dev, rk_cru_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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sc->clkdom = clkdom_create(dev);
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if (sc->clkdom == NULL)
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panic("Cannot create clkdom\n");
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for (i = 0; i < sc->nclks; i++) {
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switch (sc->clks[i].type) {
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case RK_CLK_UNDEFINED:
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break;
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case RK_CLK_PLL:
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rk_clk_pll_register(sc->clkdom, sc->clks[i].clk.pll);
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break;
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case RK_CLK_COMPOSITE:
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rk_clk_composite_register(sc->clkdom,
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sc->clks[i].clk.composite);
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break;
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case RK_CLK_MUX:
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rk_clk_mux_register(sc->clkdom, sc->clks[i].clk.mux);
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break;
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case RK_CLK_ARMCLK:
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rk_clk_armclk_register(sc->clkdom, sc->clks[i].clk.armclk);
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break;
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default:
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device_printf(dev, "Unknown clock type\n");
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return (ENXIO);
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break;
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}
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}
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if (sc->gates)
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rk_cru_register_gates(sc);
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if (clkdom_finit(sc->clkdom) != 0)
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panic("cannot finalize clkdom initialization\n");
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if (bootverbose)
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clkdom_dump(sc->clkdom);
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clk_set_assigned(dev, node);
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/* If we have resets, register our self as a reset provider */
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if (sc->resets)
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hwreset_register_ofw_provider(dev);
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return (0);
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}
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static device_method_t rk_cru_methods[] = {
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/* clkdev interface */
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DEVMETHOD(clkdev_write_4, rk_cru_write_4),
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DEVMETHOD(clkdev_read_4, rk_cru_read_4),
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DEVMETHOD(clkdev_modify_4, rk_cru_modify_4),
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DEVMETHOD(clkdev_device_lock, rk_cru_device_lock),
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DEVMETHOD(clkdev_device_unlock, rk_cru_device_unlock),
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/* Reset interface */
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DEVMETHOD(hwreset_assert, rk_cru_reset_assert),
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DEVMETHOD(hwreset_is_asserted, rk_cru_reset_is_asserted),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(rk_cru, rk_cru_driver, rk_cru_methods,
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sizeof(struct rk_cru_softc));
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